Module ctrl1

SPI control register 1

Structs

CTRL1_SPEC

SPI control register 1

Type Aliases

CLK_MODE_13_R

Field CLK_MODE_13 reader - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

CLK_MODE_13_W

Field CLK_MODE_13 writer - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].

CLK_MODE_R

Field CLK_MODE reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

CLK_MODE_W

Field CLK_MODE writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.

CS_HOLD_DELAY_R

Field CS_HOLD_DELAY reader - SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.

CS_HOLD_DELAY_W

Field CS_HOLD_DELAY writer - SPI cs signal is delayed by spi clock cycles. Can be configured in CONF state.

R

Register CTRL1 reader

RSCK_DATA_OUT_R

Field RSCK_DATA_OUT reader - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

RSCK_DATA_OUT_W

Field RSCK_DATA_OUT writer - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge

W

Register CTRL1 writer

W16_17_WR_ENA_R

Field W16_17_WR_ENA reader - 1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state.

W16_17_WR_ENA_W

Field W16_17_WR_ENA writer - 1:SPI_BUF16~SPI_BUF17 can be written 0:SPI_BUF16~SPI_BUF17 can not be written. Can be configured in CONF state.