Module esp32s2::rtc_cntl::cocpu_ctrl

ULP-RISCV configuration register

Structs

COCPU_CTRL_SPEC

ULP-RISCV configuration register

R

Register COCPU_CTRL reader

W

Register COCPU_CTRL writer

Type Definitions

COCPU_CLK_FO_R

Field COCPU_CLK_FO reader - ULP-RISCV clock force on

COCPU_CLK_FO_W

Field COCPU_CLK_FO writer - ULP-RISCV clock force on

COCPU_DONE_FORCE_R

Field COCPU_DONE_FORCE reader - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal

COCPU_DONE_FORCE_W

Field COCPU_DONE_FORCE writer - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal

COCPU_DONE_R

Field COCPU_DONE reader - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting

COCPU_DONE_W

Field COCPU_DONE writer - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting

COCPU_SEL_R

Field COCPU_SEL reader - 0: select ULP-RISCV. 1: select ULP-FSM

COCPU_SEL_W

Field COCPU_SEL writer - 0: select ULP-RISCV. 1: select ULP-FSM

COCPU_SHUT_2_CLK_DIS_R

Field COCPU_SHUT_2_CLK_DIS reader - Time from shut down ULP-RISCV to disable clock

COCPU_SHUT_2_CLK_DIS_W

Field COCPU_SHUT_2_CLK_DIS writer - Time from shut down ULP-RISCV to disable clock

COCPU_SHUT_R

Field COCPU_SHUT reader - Shut down ULP-RISCV

COCPU_SHUT_RESET_EN_R

Field COCPU_SHUT_RESET_EN reader - This bit is used to reset ULP-RISCV

COCPU_SHUT_RESET_EN_W

Field COCPU_SHUT_RESET_EN writer - This bit is used to reset ULP-RISCV

COCPU_SHUT_W

Field COCPU_SHUT writer - Shut down ULP-RISCV

COCPU_START_2_INTR_EN_R

Field COCPU_START_2_INTR_EN reader - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt

COCPU_START_2_INTR_EN_W

Field COCPU_START_2_INTR_EN writer - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt

COCPU_START_2_RESET_DIS_R

Field COCPU_START_2_RESET_DIS reader - Time from ULP-RISCV startup to pull down reset

COCPU_START_2_RESET_DIS_W

Field COCPU_START_2_RESET_DIS writer - Time from ULP-RISCV startup to pull down reset

COCPU_SW_INT_TRIGGER_W

Field COCPU_SW_INT_TRIGGER writer - Trigger ULP-RISCV register interrupt