esp32s2/uhci0/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RX_START` writer - Set this bit to clear UHCI_RX_START_INT interrupt."]
4pub type RX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TX_START` writer - Set this bit to clear UHCI_TX_START_INT interrupt."]
6pub type TX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `RX_HUNG` writer - Set this bit to clear UHCI_RX_HUNG_INT interrupt."]
8pub type RX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `TX_HUNG` writer - Set this bit to clear UHCI_TX_HUNG_INT interrupt."]
10pub type TX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `IN_DONE` writer - Set this bit to clear UHCI_IN_DONE_INT interrupt."]
12pub type IN_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `IN_SUC_EOF` writer - Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt."]
14pub type IN_SUC_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `IN_ERR_EOF` writer - Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt."]
16pub type IN_ERR_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `OUT_DONE` writer - Set this bit to clear UHCI_OUT_DONE_INT interrupt."]
18pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `OUT_EOF` writer - Set this bit to clear UHCI_OUT_EOF_INT interrupt."]
20pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `IN_DSCR_ERR` writer - Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt."]
22pub type IN_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt."]
24pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `IN_DSCR_EMPTY` writer - Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt."]
26pub type IN_DSCR_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `OUTLINK_EOF_ERR` writer - Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt."]
28pub type OUTLINK_EOF_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt."]
30pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SEND_S_REG_Q` writer - Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt."]
32pub type SEND_S_REG_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `SEND_A_REG_Q` writer - Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt."]
34pub type SEND_A_REG_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `DMA_INFIFO_FULL_WM` writer - Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt."]
36pub type DMA_INFIFO_FULL_WM_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[cfg(feature = "impl-register-debug")]
38impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
39    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
40        write!(f, "(not readable)")
41    }
42}
43impl W {
44    #[doc = "Bit 0 - Set this bit to clear UHCI_RX_START_INT interrupt."]
45    #[inline(always)]
46    pub fn rx_start(&mut self) -> RX_START_W<INT_CLR_SPEC> {
47        RX_START_W::new(self, 0)
48    }
49    #[doc = "Bit 1 - Set this bit to clear UHCI_TX_START_INT interrupt."]
50    #[inline(always)]
51    pub fn tx_start(&mut self) -> TX_START_W<INT_CLR_SPEC> {
52        TX_START_W::new(self, 1)
53    }
54    #[doc = "Bit 2 - Set this bit to clear UHCI_RX_HUNG_INT interrupt."]
55    #[inline(always)]
56    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
57        RX_HUNG_W::new(self, 2)
58    }
59    #[doc = "Bit 3 - Set this bit to clear UHCI_TX_HUNG_INT interrupt."]
60    #[inline(always)]
61    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
62        TX_HUNG_W::new(self, 3)
63    }
64    #[doc = "Bit 4 - Set this bit to clear UHCI_IN_DONE_INT interrupt."]
65    #[inline(always)]
66    pub fn in_done(&mut self) -> IN_DONE_W<INT_CLR_SPEC> {
67        IN_DONE_W::new(self, 4)
68    }
69    #[doc = "Bit 5 - Set this bit to clear UHCI_IN_SUC_EOF_INT interrupt."]
70    #[inline(always)]
71    pub fn in_suc_eof(&mut self) -> IN_SUC_EOF_W<INT_CLR_SPEC> {
72        IN_SUC_EOF_W::new(self, 5)
73    }
74    #[doc = "Bit 6 - Set this bit to clear UHCI_IN_ERR_EOF_INT interrupt."]
75    #[inline(always)]
76    pub fn in_err_eof(&mut self) -> IN_ERR_EOF_W<INT_CLR_SPEC> {
77        IN_ERR_EOF_W::new(self, 6)
78    }
79    #[doc = "Bit 7 - Set this bit to clear UHCI_OUT_DONE_INT interrupt."]
80    #[inline(always)]
81    pub fn out_done(&mut self) -> OUT_DONE_W<INT_CLR_SPEC> {
82        OUT_DONE_W::new(self, 7)
83    }
84    #[doc = "Bit 8 - Set this bit to clear UHCI_OUT_EOF_INT interrupt."]
85    #[inline(always)]
86    pub fn out_eof(&mut self) -> OUT_EOF_W<INT_CLR_SPEC> {
87        OUT_EOF_W::new(self, 8)
88    }
89    #[doc = "Bit 9 - Set this bit to clear UHCI_IN_DSCR_ERR_INT interrupt."]
90    #[inline(always)]
91    pub fn in_dscr_err(&mut self) -> IN_DSCR_ERR_W<INT_CLR_SPEC> {
92        IN_DSCR_ERR_W::new(self, 9)
93    }
94    #[doc = "Bit 10 - Set this bit to clear UHCI_OUT_DSCR_ERR_INT interrupt."]
95    #[inline(always)]
96    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<INT_CLR_SPEC> {
97        OUT_DSCR_ERR_W::new(self, 10)
98    }
99    #[doc = "Bit 11 - Set this bit to clear UHCI_IN_DSCR_EMPTY_INT interrupt."]
100    #[inline(always)]
101    pub fn in_dscr_empty(&mut self) -> IN_DSCR_EMPTY_W<INT_CLR_SPEC> {
102        IN_DSCR_EMPTY_W::new(self, 11)
103    }
104    #[doc = "Bit 12 - Set this bit to clear UHCI_OUTLINK_EOF_ERR_INT interrupt."]
105    #[inline(always)]
106    pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_CLR_SPEC> {
107        OUTLINK_EOF_ERR_W::new(self, 12)
108    }
109    #[doc = "Bit 13 - Set this bit to clear UHCI_OUT_TOTAL_EOF_INT interrupt."]
110    #[inline(always)]
111    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<INT_CLR_SPEC> {
112        OUT_TOTAL_EOF_W::new(self, 13)
113    }
114    #[doc = "Bit 14 - Set this bit to clear UHCI_SEND_S_REG_Q_INT interrupt."]
115    #[inline(always)]
116    pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_CLR_SPEC> {
117        SEND_S_REG_Q_W::new(self, 14)
118    }
119    #[doc = "Bit 15 - Set this bit to clear UHCI_SEND_A_REG_Q_INT interrupt."]
120    #[inline(always)]
121    pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_CLR_SPEC> {
122        SEND_A_REG_Q_W::new(self, 15)
123    }
124    #[doc = "Bit 16 - Set this bit to clear UHCI_DMA_INFIFO_FULL_WM_INT interrupt."]
125    #[inline(always)]
126    pub fn dma_infifo_full_wm(&mut self) -> DMA_INFIFO_FULL_WM_W<INT_CLR_SPEC> {
127        DMA_INFIFO_FULL_WM_W::new(self, 16)
128    }
129}
130#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
131pub struct INT_CLR_SPEC;
132impl crate::RegisterSpec for INT_CLR_SPEC {
133    type Ux = u32;
134}
135#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
136impl crate::Writable for INT_CLR_SPEC {
137    type Safety = crate::Unsafe;
138    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0001_ffff;
139}
140#[doc = "`reset()` method sets INT_CLR to value 0"]
141impl crate::Resettable for INT_CLR_SPEC {}
esp32s2/uhci0/int_clr.rs

esp32s2/uhci0/
int_clr.rs
