esp32s2/timg0/t/
config.rs1#[doc = "Register `CONFIG` reader"]
2pub type R = crate::R<CONFIG_SPEC>;
3#[doc = "Register `CONFIG` writer"]
4pub type W = crate::W<CONFIG_SPEC>;
5#[doc = "Field `USE_XTAL` reader - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
6pub type USE_XTAL_R = crate::BitReader;
7#[doc = "Field `USE_XTAL` writer - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
8pub type USE_XTAL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `ALARM_EN` reader - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."]
10pub type ALARM_EN_R = crate::BitReader;
11#[doc = "Field `ALARM_EN` writer - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."]
12pub type ALARM_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `LEVEL_INT_EN` reader - When set, an alarm will generate a level type interrupt."]
14pub type LEVEL_INT_EN_R = crate::BitReader;
15#[doc = "Field `LEVEL_INT_EN` writer - When set, an alarm will generate a level type interrupt."]
16pub type LEVEL_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `EDGE_INT_EN` reader - When set, an alarm will generate an edge type interrupt."]
18pub type EDGE_INT_EN_R = crate::BitReader;
19#[doc = "Field `EDGE_INT_EN` writer - When set, an alarm will generate an edge type interrupt."]
20pub type EDGE_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `DIVIDER` reader - Timer %s clock (T%s_clk) prescaler value."]
22pub type DIVIDER_R = crate::FieldReader<u16>;
23#[doc = "Field `DIVIDER` writer - Timer %s clock (T%s_clk) prescaler value."]
24pub type DIVIDER_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
25#[doc = "Field `AUTORELOAD` reader - When set, timer %s auto-reload at alarm is enabled."]
26pub type AUTORELOAD_R = crate::BitReader;
27#[doc = "Field `AUTORELOAD` writer - When set, timer %s auto-reload at alarm is enabled."]
28pub type AUTORELOAD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `INCREASE` reader - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."]
30pub type INCREASE_R = crate::BitReader;
31#[doc = "Field `INCREASE` writer - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."]
32pub type INCREASE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `EN` reader - When set, the timer %s time-base counter is enabled."]
34pub type EN_R = crate::BitReader;
35#[doc = "Field `EN` writer - When set, the timer %s time-base counter is enabled."]
36pub type EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37impl R {
38 #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
39 #[inline(always)]
40 pub fn use_xtal(&self) -> USE_XTAL_R {
41 USE_XTAL_R::new(((self.bits >> 9) & 1) != 0)
42 }
43 #[doc = "Bit 10 - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."]
44 #[inline(always)]
45 pub fn alarm_en(&self) -> ALARM_EN_R {
46 ALARM_EN_R::new(((self.bits >> 10) & 1) != 0)
47 }
48 #[doc = "Bit 11 - When set, an alarm will generate a level type interrupt."]
49 #[inline(always)]
50 pub fn level_int_en(&self) -> LEVEL_INT_EN_R {
51 LEVEL_INT_EN_R::new(((self.bits >> 11) & 1) != 0)
52 }
53 #[doc = "Bit 12 - When set, an alarm will generate an edge type interrupt."]
54 #[inline(always)]
55 pub fn edge_int_en(&self) -> EDGE_INT_EN_R {
56 EDGE_INT_EN_R::new(((self.bits >> 12) & 1) != 0)
57 }
58 #[doc = "Bits 13:28 - Timer %s clock (T%s_clk) prescaler value."]
59 #[inline(always)]
60 pub fn divider(&self) -> DIVIDER_R {
61 DIVIDER_R::new(((self.bits >> 13) & 0xffff) as u16)
62 }
63 #[doc = "Bit 29 - When set, timer %s auto-reload at alarm is enabled."]
64 #[inline(always)]
65 pub fn autoreload(&self) -> AUTORELOAD_R {
66 AUTORELOAD_R::new(((self.bits >> 29) & 1) != 0)
67 }
68 #[doc = "Bit 30 - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."]
69 #[inline(always)]
70 pub fn increase(&self) -> INCREASE_R {
71 INCREASE_R::new(((self.bits >> 30) & 1) != 0)
72 }
73 #[doc = "Bit 31 - When set, the timer %s time-base counter is enabled."]
74 #[inline(always)]
75 pub fn en(&self) -> EN_R {
76 EN_R::new(((self.bits >> 31) & 1) != 0)
77 }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for R {
81 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
82 f.debug_struct("CONFIG")
83 .field("use_xtal", &self.use_xtal())
84 .field("alarm_en", &self.alarm_en())
85 .field("level_int_en", &self.level_int_en())
86 .field("edge_int_en", &self.edge_int_en())
87 .field("divider", &self.divider())
88 .field("autoreload", &self.autoreload())
89 .field("increase", &self.increase())
90 .field("en", &self.en())
91 .finish()
92 }
93}
94impl W {
95 #[doc = "Bit 9 - 1: Use XTAL_CLK as the source clock of timer group. 0: Use APB_CLK as the source clock of timer group."]
96 #[inline(always)]
97 pub fn use_xtal(&mut self) -> USE_XTAL_W<CONFIG_SPEC> {
98 USE_XTAL_W::new(self, 9)
99 }
100 #[doc = "Bit 10 - When set, the alarm is enabled. This bit is automatically cleared once an alarm occurs."]
101 #[inline(always)]
102 pub fn alarm_en(&mut self) -> ALARM_EN_W<CONFIG_SPEC> {
103 ALARM_EN_W::new(self, 10)
104 }
105 #[doc = "Bit 11 - When set, an alarm will generate a level type interrupt."]
106 #[inline(always)]
107 pub fn level_int_en(&mut self) -> LEVEL_INT_EN_W<CONFIG_SPEC> {
108 LEVEL_INT_EN_W::new(self, 11)
109 }
110 #[doc = "Bit 12 - When set, an alarm will generate an edge type interrupt."]
111 #[inline(always)]
112 pub fn edge_int_en(&mut self) -> EDGE_INT_EN_W<CONFIG_SPEC> {
113 EDGE_INT_EN_W::new(self, 12)
114 }
115 #[doc = "Bits 13:28 - Timer %s clock (T%s_clk) prescaler value."]
116 #[inline(always)]
117 pub fn divider(&mut self) -> DIVIDER_W<CONFIG_SPEC> {
118 DIVIDER_W::new(self, 13)
119 }
120 #[doc = "Bit 29 - When set, timer %s auto-reload at alarm is enabled."]
121 #[inline(always)]
122 pub fn autoreload(&mut self) -> AUTORELOAD_W<CONFIG_SPEC> {
123 AUTORELOAD_W::new(self, 29)
124 }
125 #[doc = "Bit 30 - When set, the timer %s time-base counter will increment every clock tick. When cleared, the timer %s time-base counter will decrement."]
126 #[inline(always)]
127 pub fn increase(&mut self) -> INCREASE_W<CONFIG_SPEC> {
128 INCREASE_W::new(self, 30)
129 }
130 #[doc = "Bit 31 - When set, the timer %s time-base counter is enabled."]
131 #[inline(always)]
132 pub fn en(&mut self) -> EN_W<CONFIG_SPEC> {
133 EN_W::new(self, 31)
134 }
135}
136#[doc = "Timer 0 configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`config::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`config::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct CONFIG_SPEC;
138impl crate::RegisterSpec for CONFIG_SPEC {
139 type Ux = u32;
140}
141#[doc = "`read()` method returns [`config::R`](R) reader structure"]
142impl crate::Readable for CONFIG_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`config::W`](W) writer structure"]
144impl crate::Writable for CONFIG_SPEC {
145 type Safety = crate::Unsafe;
146}
147#[doc = "`reset()` method sets CONFIG to value 0x6000_2000"]
148impl crate::Resettable for CONFIG_SPEC {
149 const RESET_VALUE: u32 = 0x6000_2000;
150}