esp32s2/timg0/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `T(0-1)` writer - Set this bit to clear the TIMG_T%s_INT interrupt."]
4pub type T_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `WDT` writer - Set this bit to clear the TIMG_WDT_INT interrupt."]
6pub type WDT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `LACT` writer - Set this bit to clear the TIMG_LACT_INT interrupt."]
8pub type LACT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[cfg(feature = "impl-register-debug")]
10impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
11    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
12        write!(f, "(not readable)")
13    }
14}
15impl W {
16    #[doc = "Set this bit to clear the TIMG_T(0-1)_INT interrupt."]
17    #[doc = ""]
18    #[doc = "<div class=\"warning\">`n` is number of field in register. `n == 0` corresponds to `T0` field.</div>"]
19    #[inline(always)]
20    pub fn t(&mut self, n: u8) -> T_W<INT_CLR_SPEC> {
21        #[allow(clippy::no_effect)]
22        [(); 2][n as usize];
23        T_W::new(self, n)
24    }
25    #[doc = "Bit 0 - Set this bit to clear the TIMG_T0_INT interrupt."]
26    #[inline(always)]
27    pub fn t0(&mut self) -> T_W<INT_CLR_SPEC> {
28        T_W::new(self, 0)
29    }
30    #[doc = "Bit 1 - Set this bit to clear the TIMG_T1_INT interrupt."]
31    #[inline(always)]
32    pub fn t1(&mut self) -> T_W<INT_CLR_SPEC> {
33        T_W::new(self, 1)
34    }
35    #[doc = "Bit 2 - Set this bit to clear the TIMG_WDT_INT interrupt."]
36    #[inline(always)]
37    pub fn wdt(&mut self) -> WDT_W<INT_CLR_SPEC> {
38        WDT_W::new(self, 2)
39    }
40    #[doc = "Bit 3 - Set this bit to clear the TIMG_LACT_INT interrupt."]
41    #[inline(always)]
42    pub fn lact(&mut self) -> LACT_W<INT_CLR_SPEC> {
43        LACT_W::new(self, 3)
44    }
45}
46#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct INT_CLR_SPEC;
48impl crate::RegisterSpec for INT_CLR_SPEC {
49    type Ux = u32;
50}
51#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
52impl crate::Writable for INT_CLR_SPEC {
53    type Safety = crate::Unsafe;
54    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0f;
55}
56#[doc = "`reset()` method sets INT_CLR to value 0"]
57impl crate::Resettable for INT_CLR_SPEC {}
esp32s2/timg0/int_clr.rs

esp32s2/timg0/
int_clr.rs
