esp32s2/spi0/
spi_smem_ac.rs

1#[doc = "Register `SPI_SMEM_AC` reader"]
2pub type R = crate::R<SPI_SMEM_AC_SPEC>;
3#[doc = "Register `SPI_SMEM_AC` writer"]
4pub type W = crate::W<SPI_SMEM_AC_SPEC>;
5#[doc = "Field `SPI_SMEM_CS_SETUP` reader - "]
6pub type SPI_SMEM_CS_SETUP_R = crate::BitReader;
7#[doc = "Field `SPI_SMEM_CS_SETUP` writer - "]
8pub type SPI_SMEM_CS_SETUP_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SPI_SMEM_CS_HOLD` reader - "]
10pub type SPI_SMEM_CS_HOLD_R = crate::BitReader;
11#[doc = "Field `SPI_SMEM_CS_HOLD` writer - "]
12pub type SPI_SMEM_CS_HOLD_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `SPI_SMEM_CS_SETUP_TIME` reader - "]
14pub type SPI_SMEM_CS_SETUP_TIME_R = crate::FieldReader<u16>;
15#[doc = "Field `SPI_SMEM_CS_SETUP_TIME` writer - "]
16pub type SPI_SMEM_CS_SETUP_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
17#[doc = "Field `SPI_SMEM_CS_HOLD_TIME` reader - "]
18pub type SPI_SMEM_CS_HOLD_TIME_R = crate::FieldReader<u16>;
19#[doc = "Field `SPI_SMEM_CS_HOLD_TIME` writer - "]
20pub type SPI_SMEM_CS_HOLD_TIME_W<'a, REG> = crate::FieldWriter<'a, REG, 13, u16>;
21impl R {
22    #[doc = "Bit 0"]
23    #[inline(always)]
24    pub fn spi_smem_cs_setup(&self) -> SPI_SMEM_CS_SETUP_R {
25        SPI_SMEM_CS_SETUP_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1"]
28    #[inline(always)]
29    pub fn spi_smem_cs_hold(&self) -> SPI_SMEM_CS_HOLD_R {
30        SPI_SMEM_CS_HOLD_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bits 2:14"]
33    #[inline(always)]
34    pub fn spi_smem_cs_setup_time(&self) -> SPI_SMEM_CS_SETUP_TIME_R {
35        SPI_SMEM_CS_SETUP_TIME_R::new(((self.bits >> 2) & 0x1fff) as u16)
36    }
37    #[doc = "Bits 15:27"]
38    #[inline(always)]
39    pub fn spi_smem_cs_hold_time(&self) -> SPI_SMEM_CS_HOLD_TIME_R {
40        SPI_SMEM_CS_HOLD_TIME_R::new(((self.bits >> 15) & 0x1fff) as u16)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("SPI_SMEM_AC")
47            .field("spi_smem_cs_hold_time", &self.spi_smem_cs_hold_time())
48            .field("spi_smem_cs_setup_time", &self.spi_smem_cs_setup_time())
49            .field("spi_smem_cs_hold", &self.spi_smem_cs_hold())
50            .field("spi_smem_cs_setup", &self.spi_smem_cs_setup())
51            .finish()
52    }
53}
54impl W {
55    #[doc = "Bit 0"]
56    #[inline(always)]
57    pub fn spi_smem_cs_setup(&mut self) -> SPI_SMEM_CS_SETUP_W<SPI_SMEM_AC_SPEC> {
58        SPI_SMEM_CS_SETUP_W::new(self, 0)
59    }
60    #[doc = "Bit 1"]
61    #[inline(always)]
62    pub fn spi_smem_cs_hold(&mut self) -> SPI_SMEM_CS_HOLD_W<SPI_SMEM_AC_SPEC> {
63        SPI_SMEM_CS_HOLD_W::new(self, 1)
64    }
65    #[doc = "Bits 2:14"]
66    #[inline(always)]
67    pub fn spi_smem_cs_setup_time(&mut self) -> SPI_SMEM_CS_SETUP_TIME_W<SPI_SMEM_AC_SPEC> {
68        SPI_SMEM_CS_SETUP_TIME_W::new(self, 2)
69    }
70    #[doc = "Bits 15:27"]
71    #[inline(always)]
72    pub fn spi_smem_cs_hold_time(&mut self) -> SPI_SMEM_CS_HOLD_TIME_W<SPI_SMEM_AC_SPEC> {
73        SPI_SMEM_CS_HOLD_TIME_W::new(self, 15)
74    }
75}
76#[doc = "SPI Memory SRAM Access Register\n\nYou can [`read`](crate::Reg::read) this register and get [`spi_smem_ac::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`spi_smem_ac::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct SPI_SMEM_AC_SPEC;
78impl crate::RegisterSpec for SPI_SMEM_AC_SPEC {
79    type Ux = u32;
80}
81#[doc = "`read()` method returns [`spi_smem_ac::R`](R) reader structure"]
82impl crate::Readable for SPI_SMEM_AC_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`spi_smem_ac::W`](W) writer structure"]
84impl crate::Writable for SPI_SMEM_AC_SPEC {
85    type Safety = crate::Unsafe;
86}
87#[doc = "`reset()` method sets SPI_SMEM_AC to value 0"]
88impl crate::Resettable for SPI_SMEM_AC_SPEC {}
esp32s2/spi0/spi_smem_ac.rs

esp32s2/spi0/
spi_smem_ac.rs
