esp32s2/extmem/
pro_icache_autoload_cfg.rs

1#[doc = "Register `PRO_ICACHE_AUTOLOAD_CFG` reader"]
2pub type R = crate::R<PRO_ICACHE_AUTOLOAD_CFG_SPEC>;
3#[doc = "Register `PRO_ICACHE_AUTOLOAD_CFG` writer"]
4pub type W = crate::W<PRO_ICACHE_AUTOLOAD_CFG_SPEC>;
5#[doc = "Field `PRO_ICACHE_AUTOLOAD_MODE` reader - Reserved."]
6pub type PRO_ICACHE_AUTOLOAD_MODE_R = crate::BitReader;
7#[doc = "Field `PRO_ICACHE_AUTOLOAD_MODE` writer - Reserved."]
8pub type PRO_ICACHE_AUTOLOAD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PRO_ICACHE_AUTOLOAD_STEP` reader - Reserved."]
10pub type PRO_ICACHE_AUTOLOAD_STEP_R = crate::FieldReader;
11#[doc = "Field `PRO_ICACHE_AUTOLOAD_STEP` writer - Reserved."]
12pub type PRO_ICACHE_AUTOLOAD_STEP_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13#[doc = "Field `PRO_ICACHE_AUTOLOAD_ORDER` reader - The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending."]
14pub type PRO_ICACHE_AUTOLOAD_ORDER_R = crate::BitReader;
15#[doc = "Field `PRO_ICACHE_AUTOLOAD_ORDER` writer - The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending."]
16pub type PRO_ICACHE_AUTOLOAD_ORDER_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PRO_ICACHE_AUTOLOAD_RQST` reader - The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
18pub type PRO_ICACHE_AUTOLOAD_RQST_R = crate::FieldReader;
19#[doc = "Field `PRO_ICACHE_AUTOLOAD_RQST` writer - The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
20pub type PRO_ICACHE_AUTOLOAD_RQST_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `PRO_ICACHE_AUTOLOAD_SIZE` reader - The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation."]
22pub type PRO_ICACHE_AUTOLOAD_SIZE_R = crate::FieldReader;
23#[doc = "Field `PRO_ICACHE_AUTOLOAD_SIZE` writer - The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation."]
24pub type PRO_ICACHE_AUTOLOAD_SIZE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25#[doc = "Field `PRO_ICACHE_AUTOLOAD_SCT0_ENA` reader - The bits are used to enable the second section for conditional pre-load operation."]
26pub type PRO_ICACHE_AUTOLOAD_SCT0_ENA_R = crate::BitReader;
27#[doc = "Field `PRO_ICACHE_AUTOLOAD_SCT0_ENA` writer - The bits are used to enable the second section for conditional pre-load operation."]
28pub type PRO_ICACHE_AUTOLOAD_SCT0_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `PRO_ICACHE_AUTOLOAD_SCT1_ENA` reader - The bits are used to enable the first section for conditional pre-load operation."]
30pub type PRO_ICACHE_AUTOLOAD_SCT1_ENA_R = crate::BitReader;
31#[doc = "Field `PRO_ICACHE_AUTOLOAD_SCT1_ENA` writer - The bits are used to enable the first section for conditional pre-load operation."]
32pub type PRO_ICACHE_AUTOLOAD_SCT1_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - Reserved."]
35    #[inline(always)]
36    pub fn pro_icache_autoload_mode(&self) -> PRO_ICACHE_AUTOLOAD_MODE_R {
37        PRO_ICACHE_AUTOLOAD_MODE_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bits 1:2 - Reserved."]
40    #[inline(always)]
41    pub fn pro_icache_autoload_step(&self) -> PRO_ICACHE_AUTOLOAD_STEP_R {
42        PRO_ICACHE_AUTOLOAD_STEP_R::new(((self.bits >> 1) & 3) as u8)
43    }
44    #[doc = "Bit 3 - The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending."]
45    #[inline(always)]
46    pub fn pro_icache_autoload_order(&self) -> PRO_ICACHE_AUTOLOAD_ORDER_R {
47        PRO_ICACHE_AUTOLOAD_ORDER_R::new(((self.bits >> 3) & 1) != 0)
48    }
49    #[doc = "Bits 4:5 - The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
50    #[inline(always)]
51    pub fn pro_icache_autoload_rqst(&self) -> PRO_ICACHE_AUTOLOAD_RQST_R {
52        PRO_ICACHE_AUTOLOAD_RQST_R::new(((self.bits >> 4) & 3) as u8)
53    }
54    #[doc = "Bits 6:7 - The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation."]
55    #[inline(always)]
56    pub fn pro_icache_autoload_size(&self) -> PRO_ICACHE_AUTOLOAD_SIZE_R {
57        PRO_ICACHE_AUTOLOAD_SIZE_R::new(((self.bits >> 6) & 3) as u8)
58    }
59    #[doc = "Bit 8 - The bits are used to enable the second section for conditional pre-load operation."]
60    #[inline(always)]
61    pub fn pro_icache_autoload_sct0_ena(&self) -> PRO_ICACHE_AUTOLOAD_SCT0_ENA_R {
62        PRO_ICACHE_AUTOLOAD_SCT0_ENA_R::new(((self.bits >> 8) & 1) != 0)
63    }
64    #[doc = "Bit 9 - The bits are used to enable the first section for conditional pre-load operation."]
65    #[inline(always)]
66    pub fn pro_icache_autoload_sct1_ena(&self) -> PRO_ICACHE_AUTOLOAD_SCT1_ENA_R {
67        PRO_ICACHE_AUTOLOAD_SCT1_ENA_R::new(((self.bits >> 9) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("PRO_ICACHE_AUTOLOAD_CFG")
74            .field("pro_icache_autoload_mode", &self.pro_icache_autoload_mode())
75            .field("pro_icache_autoload_step", &self.pro_icache_autoload_step())
76            .field(
77                "pro_icache_autoload_order",
78                &self.pro_icache_autoload_order(),
79            )
80            .field("pro_icache_autoload_rqst", &self.pro_icache_autoload_rqst())
81            .field("pro_icache_autoload_size", &self.pro_icache_autoload_size())
82            .field(
83                "pro_icache_autoload_sct0_ena",
84                &self.pro_icache_autoload_sct0_ena(),
85            )
86            .field(
87                "pro_icache_autoload_sct1_ena",
88                &self.pro_icache_autoload_sct1_ena(),
89            )
90            .finish()
91    }
92}
93impl W {
94    #[doc = "Bit 0 - Reserved."]
95    #[inline(always)]
96    pub fn pro_icache_autoload_mode(
97        &mut self,
98    ) -> PRO_ICACHE_AUTOLOAD_MODE_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
99        PRO_ICACHE_AUTOLOAD_MODE_W::new(self, 0)
100    }
101    #[doc = "Bits 1:2 - Reserved."]
102    #[inline(always)]
103    pub fn pro_icache_autoload_step(
104        &mut self,
105    ) -> PRO_ICACHE_AUTOLOAD_STEP_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
106        PRO_ICACHE_AUTOLOAD_STEP_W::new(self, 1)
107    }
108    #[doc = "Bit 3 - The bits are used to configure the direction of conditional pre-load operation. 1: descending, 0: ascending."]
109    #[inline(always)]
110    pub fn pro_icache_autoload_order(
111        &mut self,
112    ) -> PRO_ICACHE_AUTOLOAD_ORDER_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
113        PRO_ICACHE_AUTOLOAD_ORDER_W::new(self, 3)
114    }
115    #[doc = "Bits 4:5 - The bits are used to configure trigger conditions for conditional pre-load. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit."]
116    #[inline(always)]
117    pub fn pro_icache_autoload_rqst(
118        &mut self,
119    ) -> PRO_ICACHE_AUTOLOAD_RQST_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
120        PRO_ICACHE_AUTOLOAD_RQST_W::new(self, 4)
121    }
122    #[doc = "Bits 6:7 - The bits are used to configure the numbers of the cache block for the issuing conditional pre-load operation."]
123    #[inline(always)]
124    pub fn pro_icache_autoload_size(
125        &mut self,
126    ) -> PRO_ICACHE_AUTOLOAD_SIZE_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
127        PRO_ICACHE_AUTOLOAD_SIZE_W::new(self, 6)
128    }
129    #[doc = "Bit 8 - The bits are used to enable the second section for conditional pre-load operation."]
130    #[inline(always)]
131    pub fn pro_icache_autoload_sct0_ena(
132        &mut self,
133    ) -> PRO_ICACHE_AUTOLOAD_SCT0_ENA_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
134        PRO_ICACHE_AUTOLOAD_SCT0_ENA_W::new(self, 8)
135    }
136    #[doc = "Bit 9 - The bits are used to enable the first section for conditional pre-load operation."]
137    #[inline(always)]
138    pub fn pro_icache_autoload_sct1_ena(
139        &mut self,
140    ) -> PRO_ICACHE_AUTOLOAD_SCT1_ENA_W<PRO_ICACHE_AUTOLOAD_CFG_SPEC> {
141        PRO_ICACHE_AUTOLOAD_SCT1_ENA_W::new(self, 9)
142    }
143}
144#[doc = "register description\n\nYou can [`read`](crate::Reg::read) this register and get [`pro_icache_autoload_cfg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pro_icache_autoload_cfg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
145pub struct PRO_ICACHE_AUTOLOAD_CFG_SPEC;
146impl crate::RegisterSpec for PRO_ICACHE_AUTOLOAD_CFG_SPEC {
147    type Ux = u32;
148}
149#[doc = "`read()` method returns [`pro_icache_autoload_cfg::R`](R) reader structure"]
150impl crate::Readable for PRO_ICACHE_AUTOLOAD_CFG_SPEC {}
151#[doc = "`write(|w| ..)` method takes [`pro_icache_autoload_cfg::W`](W) writer structure"]
152impl crate::Writable for PRO_ICACHE_AUTOLOAD_CFG_SPEC {
153    type Safety = crate::Unsafe;
154}
155#[doc = "`reset()` method sets PRO_ICACHE_AUTOLOAD_CFG to value 0"]
156impl crate::Resettable for PRO_ICACHE_AUTOLOAD_CFG_SPEC {}
esp32s2/extmem/pro_icache_autoload_cfg.rs

esp32s2/extmem/
pro_icache_autoload_cfg.rs
