1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `SDA_FORCE_OUT` reader - SDA output mode. 0: open drain. 1: push pull."]
6pub type SDA_FORCE_OUT_R = crate::BitReader;
7#[doc = "Field `SDA_FORCE_OUT` writer - SDA output mode. 0: open drain. 1: push pull."]
8pub type SDA_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `SCL_FORCE_OUT` reader - SCL output mode. 0: open drain. 1: push pull."]
10pub type SCL_FORCE_OUT_R = crate::BitReader;
11#[doc = "Field `SCL_FORCE_OUT` writer - SCL output mode. 0: open drain. 1: push pull."]
12pub type SCL_FORCE_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MS_MODE` reader - Set this bit to configure RTC I²C as a master."]
14pub type MS_MODE_R = crate::BitReader;
15#[doc = "Field `MS_MODE` writer - Set this bit to configure RTC I²C as a master."]
16pub type MS_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `TRANS_START` reader - Set this bit to 1, RTC I2C starts sending data."]
18pub type TRANS_START_R = crate::BitReader;
19#[doc = "Field `TRANS_START` writer - Set this bit to 1, RTC I2C starts sending data."]
20pub type TRANS_START_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TX_LSB_FIRST` reader - This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit."]
22pub type TX_LSB_FIRST_R = crate::BitReader;
23#[doc = "Field `TX_LSB_FIRST` writer - This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit."]
24pub type TX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `RX_LSB_FIRST` reader - This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit."]
26pub type RX_LSB_FIRST_R = crate::BitReader;
27#[doc = "Field `RX_LSB_FIRST` writer - This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit."]
28pub type RX_LSB_FIRST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CLK_GATE_EN` reader - RTC I²C controller clock gate."]
30pub type CLK_GATE_EN_R = crate::BitReader;
31#[doc = "Field `CLK_GATE_EN` writer - RTC I²C controller clock gate."]
32pub type CLK_GATE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `RESET` reader - RTC I²C software reset."]
34pub type RESET_R = crate::BitReader;
35#[doc = "Field `RESET` writer - RTC I²C software reset."]
36pub type RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CLK_EN` reader - rtc i2c reg clk gating"]
38pub type CLK_EN_R = crate::BitReader;
39#[doc = "Field `CLK_EN` writer - rtc i2c reg clk gating"]
40pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42 #[doc = "Bit 0 - SDA output mode. 0: open drain. 1: push pull."]
43 #[inline(always)]
44 pub fn sda_force_out(&self) -> SDA_FORCE_OUT_R {
45 SDA_FORCE_OUT_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - SCL output mode. 0: open drain. 1: push pull."]
48 #[inline(always)]
49 pub fn scl_force_out(&self) -> SCL_FORCE_OUT_R {
50 SCL_FORCE_OUT_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - Set this bit to configure RTC I²C as a master."]
53 #[inline(always)]
54 pub fn ms_mode(&self) -> MS_MODE_R {
55 MS_MODE_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 3 - Set this bit to 1, RTC I2C starts sending data."]
58 #[inline(always)]
59 pub fn trans_start(&self) -> TRANS_START_R {
60 TRANS_START_R::new(((self.bits >> 3) & 1) != 0)
61 }
62 #[doc = "Bit 4 - This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit."]
63 #[inline(always)]
64 pub fn tx_lsb_first(&self) -> TX_LSB_FIRST_R {
65 TX_LSB_FIRST_R::new(((self.bits >> 4) & 1) != 0)
66 }
67 #[doc = "Bit 5 - This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit."]
68 #[inline(always)]
69 pub fn rx_lsb_first(&self) -> RX_LSB_FIRST_R {
70 RX_LSB_FIRST_R::new(((self.bits >> 5) & 1) != 0)
71 }
72 #[doc = "Bit 29 - RTC I²C controller clock gate."]
73 #[inline(always)]
74 pub fn clk_gate_en(&self) -> CLK_GATE_EN_R {
75 CLK_GATE_EN_R::new(((self.bits >> 29) & 1) != 0)
76 }
77 #[doc = "Bit 30 - RTC I²C software reset."]
78 #[inline(always)]
79 pub fn reset(&self) -> RESET_R {
80 RESET_R::new(((self.bits >> 30) & 1) != 0)
81 }
82 #[doc = "Bit 31 - rtc i2c reg clk gating"]
83 #[inline(always)]
84 pub fn clk_en(&self) -> CLK_EN_R {
85 CLK_EN_R::new(((self.bits >> 31) & 1) != 0)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("CTRL")
92 .field("sda_force_out", &self.sda_force_out())
93 .field("scl_force_out", &self.scl_force_out())
94 .field("ms_mode", &self.ms_mode())
95 .field("trans_start", &self.trans_start())
96 .field("tx_lsb_first", &self.tx_lsb_first())
97 .field("rx_lsb_first", &self.rx_lsb_first())
98 .field("clk_gate_en", &self.clk_gate_en())
99 .field("reset", &self.reset())
100 .field("clk_en", &self.clk_en())
101 .finish()
102 }
103}
104impl W {
105 #[doc = "Bit 0 - SDA output mode. 0: open drain. 1: push pull."]
106 #[inline(always)]
107 pub fn sda_force_out(&mut self) -> SDA_FORCE_OUT_W<CTRL_SPEC> {
108 SDA_FORCE_OUT_W::new(self, 0)
109 }
110 #[doc = "Bit 1 - SCL output mode. 0: open drain. 1: push pull."]
111 #[inline(always)]
112 pub fn scl_force_out(&mut self) -> SCL_FORCE_OUT_W<CTRL_SPEC> {
113 SCL_FORCE_OUT_W::new(self, 1)
114 }
115 #[doc = "Bit 2 - Set this bit to configure RTC I²C as a master."]
116 #[inline(always)]
117 pub fn ms_mode(&mut self) -> MS_MODE_W<CTRL_SPEC> {
118 MS_MODE_W::new(self, 2)
119 }
120 #[doc = "Bit 3 - Set this bit to 1, RTC I2C starts sending data."]
121 #[inline(always)]
122 pub fn trans_start(&mut self) -> TRANS_START_W<CTRL_SPEC> {
123 TRANS_START_W::new(self, 3)
124 }
125 #[doc = "Bit 4 - This bit is used to control the sending mode. 0: send data from the most significant bit. 1: send data from the least significant bit."]
126 #[inline(always)]
127 pub fn tx_lsb_first(&mut self) -> TX_LSB_FIRST_W<CTRL_SPEC> {
128 TX_LSB_FIRST_W::new(self, 4)
129 }
130 #[doc = "Bit 5 - This bit is used to control the storage mode for received data. 0: receive data from the most significant bit. 1: receive data from the least significant bit."]
131 #[inline(always)]
132 pub fn rx_lsb_first(&mut self) -> RX_LSB_FIRST_W<CTRL_SPEC> {
133 RX_LSB_FIRST_W::new(self, 5)
134 }
135 #[doc = "Bit 29 - RTC I²C controller clock gate."]
136 #[inline(always)]
137 pub fn clk_gate_en(&mut self) -> CLK_GATE_EN_W<CTRL_SPEC> {
138 CLK_GATE_EN_W::new(self, 29)
139 }
140 #[doc = "Bit 30 - RTC I²C software reset."]
141 #[inline(always)]
142 pub fn reset(&mut self) -> RESET_W<CTRL_SPEC> {
143 RESET_W::new(self, 30)
144 }
145 #[doc = "Bit 31 - rtc i2c reg clk gating"]
146 #[inline(always)]
147 pub fn clk_en(&mut self) -> CLK_EN_W<CTRL_SPEC> {
148 CLK_EN_W::new(self, 31)
149 }
150}
151#[doc = "Transmission setting\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
152pub struct CTRL_SPEC;
153impl crate::RegisterSpec for CTRL_SPEC {
154 type Ux = u32;
155}
156#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
157impl crate::Readable for CTRL_SPEC {}
158#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
159impl crate::Writable for CTRL_SPEC {
160 type Safety = crate::Unsafe;
161 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
162 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
163}
164#[doc = "`reset()` method sets CTRL to value 0"]
165impl crate::Resettable for CTRL_SPEC {
166 const RESET_VALUE: u32 = 0;
167}