esp32s2::gpio

Module pin

Source
Expand description

Configuration for GPIO pin %s

Structs§

Type Aliases§

  • CONFIG_R
    Field CONFIG reader - Reserved
  • CONFIG_W
    Field CONFIG writer - Reserved
  • INT_ENA_R
    Field INT_ENA reader - Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled.
  • INT_ENA_W
    Field INT_ENA writer - Interrupt enable bits. bit13: CPU interrupt enabled; bit14: CPU non-maskable interrupt enabled.
  • INT_TYPE_R
    Field INT_TYPE reader - Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)
  • INT_TYPE_W
    Field INT_TYPE writer - Interrupt type selection. 0: GPIO interrupt disabled; 1: rising edge trigger; 2: falling edge trigger; 3: any edge trigger; 4: low level trigger; 5: high level trigger. (R/W)
  • PAD_DRIVER_R
    Field PAD_DRIVER reader - Pad driver selection. 0: normal output; 1: open drain output..
  • PAD_DRIVER_W
    Field PAD_DRIVER writer - Pad driver selection. 0: normal output; 1: open drain output..
  • R
    Register PIN%s reader
  • SYNC1_BYPASS_R
    Field SYNC1_BYPASS reader - For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.
  • SYNC1_BYPASS_W
    Field SYNC1_BYPASS writer - For the first stage synchronization, GPIO input data can be synchro- nized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.
  • SYNC2_BYPASS_R
    Field SYNC2_BYPASS reader - For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.
  • SYNC2_BYPASS_W
    Field SYNC2_BYPASS writer - For the second stage synchronization, GPIO input data can be syn- chronized on either edge of the APB clock. 0: no synchronization; 1: synchronized on falling edge; 2 and 3: synchronized on rising edge.
  • W
    Register PIN%s writer
  • WAKEUP_ENABLE_R
    Field WAKEUP_ENABLE reader - GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.
  • WAKEUP_ENABLE_W
    Field WAKEUP_ENABLE writer - GPIO wake-up enable bit, only wakes up the CPU from Light-sleep.