1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246

#[doc = "Register `SLAVE` reader"]
pub type R = crate::R<SLAVE_SPEC>;
#[doc = "Register `SLAVE` writer"]
pub type W = crate::W<SLAVE_SPEC>;
#[doc = "Field `TRANS_DONE` reader - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf."]
pub type TRANS_DONE_R = crate::BitReader;
#[doc = "Field `TRANS_DONE` writer - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf."]
pub type TRANS_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_RD_BUF_DONE_EN` reader - SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_RD_BUF_DONE_EN_R = crate::BitReader;
#[doc = "Field `INT_RD_BUF_DONE_EN` writer - SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_RD_BUF_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_WR_BUF_DONE_EN` reader - SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_WR_BUF_DONE_EN_R = crate::BitReader;
#[doc = "Field `INT_WR_BUF_DONE_EN` writer - SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_WR_BUF_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_RD_DMA_DONE_EN` reader - SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_RD_DMA_DONE_EN_R = crate::BitReader;
#[doc = "Field `INT_RD_DMA_DONE_EN` writer - SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_RD_DMA_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_WR_DMA_DONE_EN` reader - SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_WR_DMA_DONE_EN_R = crate::BitReader;
#[doc = "Field `INT_WR_DMA_DONE_EN` writer - SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_WR_DMA_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_TRANS_DONE_EN` reader - SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_TRANS_DONE_EN_R = crate::BitReader;
#[doc = "Field `INT_TRANS_DONE_EN` writer - SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_TRANS_DONE_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `INT_DMA_SEG_TRANS_EN` reader - SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_DMA_SEG_TRANS_EN_R = crate::BitReader;
#[doc = "Field `INT_DMA_SEG_TRANS_EN` writer - SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
pub type INT_DMA_SEG_TRANS_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SEG_MAGIC_ERR_INT_EN` reader - 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state."]
pub type SEG_MAGIC_ERR_INT_EN_R = crate::BitReader;
#[doc = "Field `SEG_MAGIC_ERR_INT_EN` writer - 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state."]
pub type SEG_MAGIC_ERR_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `TRANS_CNT` reader - The operations counter in both the master mode and the slave mode."]
pub type TRANS_CNT_R = crate::FieldReader;
#[doc = "Field `TRANS_DONE_AUTO_CLR_EN` reader - SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state."]
pub type TRANS_DONE_AUTO_CLR_EN_R = crate::BitReader;
#[doc = "Field `TRANS_DONE_AUTO_CLR_EN` writer - SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state."]
pub type TRANS_DONE_AUTO_CLR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `MODE` reader - Set SPI work mode. 1: slave mode 0: master mode."]
pub type MODE_R = crate::BitReader;
#[doc = "Field `MODE` writer - Set SPI work mode. 1: slave mode 0: master mode."]
pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
#[doc = "Field `SOFT_RESET` reader - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
pub type SOFT_RESET_R = crate::BitReader;
#[doc = "Field `SOFT_RESET` writer - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
pub type SOFT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
impl R {
    #[doc = "Bit 4 - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf."]
    #[inline(always)]
    pub fn trans_done(&self) -> TRANS_DONE_R {
        TRANS_DONE_R::new(((self.bits >> 4) & 1) != 0)
    }
    #[doc = "Bit 5 - SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    pub fn int_rd_buf_done_en(&self) -> INT_RD_BUF_DONE_EN_R {
        INT_RD_BUF_DONE_EN_R::new(((self.bits >> 5) & 1) != 0)
    }
    #[doc = "Bit 6 - SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    pub fn int_wr_buf_done_en(&self) -> INT_WR_BUF_DONE_EN_R {
        INT_WR_BUF_DONE_EN_R::new(((self.bits >> 6) & 1) != 0)
    }
    #[doc = "Bit 7 - SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    pub fn int_rd_dma_done_en(&self) -> INT_RD_DMA_DONE_EN_R {
        INT_RD_DMA_DONE_EN_R::new(((self.bits >> 7) & 1) != 0)
    }
    #[doc = "Bit 8 - SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    pub fn int_wr_dma_done_en(&self) -> INT_WR_DMA_DONE_EN_R {
        INT_WR_DMA_DONE_EN_R::new(((self.bits >> 8) & 1) != 0)
    }
    #[doc = "Bit 9 - SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    pub fn int_trans_done_en(&self) -> INT_TRANS_DONE_EN_R {
        INT_TRANS_DONE_EN_R::new(((self.bits >> 9) & 1) != 0)
    }
    #[doc = "Bit 10 - SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    pub fn int_dma_seg_trans_en(&self) -> INT_DMA_SEG_TRANS_EN_R {
        INT_DMA_SEG_TRANS_EN_R::new(((self.bits >> 10) & 1) != 0)
    }
    #[doc = "Bit 11 - 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state."]
    #[inline(always)]
    pub fn seg_magic_err_int_en(&self) -> SEG_MAGIC_ERR_INT_EN_R {
        SEG_MAGIC_ERR_INT_EN_R::new(((self.bits >> 11) & 1) != 0)
    }
    #[doc = "Bits 23:26 - The operations counter in both the master mode and the slave mode."]
    #[inline(always)]
    pub fn trans_cnt(&self) -> TRANS_CNT_R {
        TRANS_CNT_R::new(((self.bits >> 23) & 0x0f) as u8)
    }
    #[doc = "Bit 29 - SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state."]
    #[inline(always)]
    pub fn trans_done_auto_clr_en(&self) -> TRANS_DONE_AUTO_CLR_EN_R {
        TRANS_DONE_AUTO_CLR_EN_R::new(((self.bits >> 29) & 1) != 0)
    }
    #[doc = "Bit 30 - Set SPI work mode. 1: slave mode 0: master mode."]
    #[inline(always)]
    pub fn mode(&self) -> MODE_R {
        MODE_R::new(((self.bits >> 30) & 1) != 0)
    }
    #[doc = "Bit 31 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
    #[inline(always)]
    pub fn soft_reset(&self) -> SOFT_RESET_R {
        SOFT_RESET_R::new(((self.bits >> 31) & 1) != 0)
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for R {
    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
        f.debug_struct("SLAVE")
            .field("trans_done", &format_args!("{}", self.trans_done().bit()))
            .field(
                "int_rd_buf_done_en",
                &format_args!("{}", self.int_rd_buf_done_en().bit()),
            )
            .field(
                "int_wr_buf_done_en",
                &format_args!("{}", self.int_wr_buf_done_en().bit()),
            )
            .field(
                "int_rd_dma_done_en",
                &format_args!("{}", self.int_rd_dma_done_en().bit()),
            )
            .field(
                "int_wr_dma_done_en",
                &format_args!("{}", self.int_wr_dma_done_en().bit()),
            )
            .field(
                "int_trans_done_en",
                &format_args!("{}", self.int_trans_done_en().bit()),
            )
            .field(
                "int_dma_seg_trans_en",
                &format_args!("{}", self.int_dma_seg_trans_en().bit()),
            )
            .field(
                "seg_magic_err_int_en",
                &format_args!("{}", self.seg_magic_err_int_en().bit()),
            )
            .field("trans_cnt", &format_args!("{}", self.trans_cnt().bits()))
            .field(
                "trans_done_auto_clr_en",
                &format_args!("{}", self.trans_done_auto_clr_en().bit()),
            )
            .field("mode", &format_args!("{}", self.mode().bit()))
            .field("soft_reset", &format_args!("{}", self.soft_reset().bit()))
            .finish()
    }
}
#[cfg(feature = "impl-register-debug")]
impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
        core::fmt::Debug::fmt(&self.read(), f)
    }
}
impl W {
    #[doc = "Bit 4 - The interrupt raw bit for the completion of any operation in both the master mode and the slave mode. Can not be changed by CONF_buf."]
    #[inline(always)]
    #[must_use]
    pub fn trans_done(&mut self) -> TRANS_DONE_W<SLAVE_SPEC> {
        TRANS_DONE_W::new(self, 4)
    }
    #[doc = "Bit 5 - SPI_SLV_RD_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn int_rd_buf_done_en(&mut self) -> INT_RD_BUF_DONE_EN_W<SLAVE_SPEC> {
        INT_RD_BUF_DONE_EN_W::new(self, 5)
    }
    #[doc = "Bit 6 - SPI_SLV_WR_BUF_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn int_wr_buf_done_en(&mut self) -> INT_WR_BUF_DONE_EN_W<SLAVE_SPEC> {
        INT_WR_BUF_DONE_EN_W::new(self, 6)
    }
    #[doc = "Bit 7 - SPI_SLV_RD_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn int_rd_dma_done_en(&mut self) -> INT_RD_DMA_DONE_EN_W<SLAVE_SPEC> {
        INT_RD_DMA_DONE_EN_W::new(self, 7)
    }
    #[doc = "Bit 8 - SPI_SLV_WR_DMA_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn int_wr_dma_done_en(&mut self) -> INT_WR_DMA_DONE_EN_W<SLAVE_SPEC> {
        INT_WR_DMA_DONE_EN_W::new(self, 8)
    }
    #[doc = "Bit 9 - SPI_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn int_trans_done_en(&mut self) -> INT_TRANS_DONE_EN_W<SLAVE_SPEC> {
        INT_TRANS_DONE_EN_W::new(self, 9)
    }
    #[doc = "Bit 10 - SPI_DMA_SEG_TRANS_DONE Interrupt enable. 1: enable 0: disable. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn int_dma_seg_trans_en(&mut self) -> INT_DMA_SEG_TRANS_EN_W<SLAVE_SPEC> {
        INT_DMA_SEG_TRANS_EN_W::new(self, 10)
    }
    #[doc = "Bit 11 - 1: Enable seg magic value error interrupt. 0: Others. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn seg_magic_err_int_en(&mut self) -> SEG_MAGIC_ERR_INT_EN_W<SLAVE_SPEC> {
        SEG_MAGIC_ERR_INT_EN_W::new(self, 11)
    }
    #[doc = "Bit 29 - SPI_TRANS_DONE auto clear enable, clear it 3 apb cycles after the pos edge of SPI_TRANS_DONE. 0:disable. 1: enable. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn trans_done_auto_clr_en(&mut self) -> TRANS_DONE_AUTO_CLR_EN_W<SLAVE_SPEC> {
        TRANS_DONE_AUTO_CLR_EN_W::new(self, 29)
    }
    #[doc = "Bit 30 - Set SPI work mode. 1: slave mode 0: master mode."]
    #[inline(always)]
    #[must_use]
    pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
        MODE_W::new(self, 30)
    }
    #[doc = "Bit 31 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
    #[inline(always)]
    #[must_use]
    pub fn soft_reset(&mut self) -> SOFT_RESET_W<SLAVE_SPEC> {
        SOFT_RESET_W::new(self, 31)
    }
}
#[doc = "SPI slave control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct SLAVE_SPEC;
impl crate::RegisterSpec for SLAVE_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [`slave::R`](R) reader structure"]
impl crate::Readable for SLAVE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`slave::W`](W) writer structure"]
impl crate::Writable for SLAVE_SPEC {
    type Safety = crate::Unsafe;
    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
#[doc = "`reset()` method sets SLAVE to value 0x0200"]
impl crate::Resettable for SLAVE_SPEC {
    const RESET_VALUE: u32 = 0x0200;
}