Expand description
Configuration register 1
Structs§
- Configuration register 1
Type Aliases§
- Register
CONF1reader - Field
RXFIFO_FULL_THRHDreader - An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value. - Field
RXFIFO_FULL_THRHDwriter - An UART_RXFIFO_FULL_INT interrupt is generated when the receiver receives more data than this register’s value. - Field
RX_FLOW_ENreader - This is the flow enable bit for UART receiver. 1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control. - Field
RX_FLOW_ENwriter - This is the flow enable bit for UART receiver. 1: Choose software flow control with configuring sw_rts signal. 0: Disable software flow control. - Field
RX_TOUT_ENreader - This is the enable bit for UART receiver’s timeout function. - Field
RX_TOUT_ENwriter - This is the enable bit for UART receiver’s timeout function. - Field
RX_TOUT_FLOW_DISreader - Set this bit to stop accumulating idle_cnt when hardware flow control works. - Field
RX_TOUT_FLOW_DISwriter - Set this bit to stop accumulating idle_cnt when hardware flow control works. - Field
TXFIFO_EMPTY_THRHDreader - An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register’s value. - Field
TXFIFO_EMPTY_THRHDwriter - An UART_TXFIFO_EMPTY_INT interrupt is generated when the number of data bytes in TX FIFO is less than this register’s value. - Register
CONF1writer