Module esp32s2::uhci0::conf0

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Expand description

UHCI configuration register

Structs

Type Aliases

  • AHBM_FIFO_RST_R
    Field AHBM_FIFO_RST reader - Set this bit to reset AHB interface cmdFIFO of DMA.
  • AHBM_FIFO_RST_W
    Field AHBM_FIFO_RST writer - Set this bit to reset AHB interface cmdFIFO of DMA.
  • AHBM_RST_R
    Field AHBM_RST reader - Set this bit to reset AHB interface of DMA.
  • AHBM_RST_W
    Field AHBM_RST writer - Set this bit to reset AHB interface of DMA.
  • CLK_EN_R
    Field CLK_EN reader - 1: Force clock on for registers. 0: Support clock only when application writes registers.
  • CLK_EN_W
    Field CLK_EN writer - 1: Force clock on for registers. 0: Support clock only when application writes registers.
  • CRC_REC_EN_R
    Field CRC_REC_EN reader - Set this bit to enable UHCI to receive the 16 bit CRC.
  • CRC_REC_EN_W
    Field CRC_REC_EN writer - Set this bit to enable UHCI to receive the 16 bit CRC.
  • ENCODE_CRC_EN_R
    Field ENCODE_CRC_EN reader - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload.
  • ENCODE_CRC_EN_W
    Field ENCODE_CRC_EN writer - Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload.
  • HEAD_EN_R
    Field HEAD_EN reader - Set this bit to encode the data packet with a formatting header.
  • HEAD_EN_W
    Field HEAD_EN writer - Set this bit to encode the data packet with a formatting header.
  • INDSCR_BURST_EN_R
    Field INDSCR_BURST_EN reader - This register is used to specify DMA receive descriptor transfer mode. 1: burst mode. 0: byte mode.
  • INDSCR_BURST_EN_W
    Field INDSCR_BURST_EN writer - This register is used to specify DMA receive descriptor transfer mode. 1: burst mode. 0: byte mode.
  • IN_LOOP_TEST_R
    Field IN_LOOP_TEST reader - Reserved.
  • IN_LOOP_TEST_W
    Field IN_LOOP_TEST writer - Reserved.
  • IN_RST_R
    Field IN_RST reader - Set this bit to reset in DMA FSM.
  • IN_RST_W
    Field IN_RST writer - Set this bit to reset in DMA FSM.
  • LEN_EOF_EN_R
    Field LEN_EOF_EN reader - If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0.
  • LEN_EOF_EN_W
    Field LEN_EOF_EN writer - If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0.
  • MEM_TRANS_EN_R
    Field MEM_TRANS_EN reader - 1: UHCI transmitted data would be write back into DMA INFIFO.
  • MEM_TRANS_EN_W
    Field MEM_TRANS_EN writer - 1: UHCI transmitted data would be write back into DMA INFIFO.
  • OUTDSCR_BURST_EN_R
    Field OUTDSCR_BURST_EN reader - This register is used to specify DMA transmit descriptor transfer mode. 1: burst mode. 0: byte mode.
  • OUTDSCR_BURST_EN_W
    Field OUTDSCR_BURST_EN writer - This register is used to specify DMA transmit descriptor transfer mode. 1: burst mode. 0: byte mode.
  • OUT_AUTO_WRBACK_R
    Field OUT_AUTO_WRBACK reader - Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted.
  • OUT_AUTO_WRBACK_W
    Field OUT_AUTO_WRBACK writer - Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted.
  • OUT_EOF_MODE_R
    Field OUT_EOF_MODE reader - This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. 1: When DMA has popped all data from FIFO. 0: When AHB has pushed all data to FIFO.
  • OUT_EOF_MODE_W
    Field OUT_EOF_MODE writer - This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. 1: When DMA has popped all data from FIFO. 0: When AHB has pushed all data to FIFO.
  • OUT_LOOP_TEST_R
    Field OUT_LOOP_TEST reader - Reserved.
  • OUT_LOOP_TEST_W
    Field OUT_LOOP_TEST writer - Reserved.
  • OUT_NO_RESTART_CLR_R
    Field OUT_NO_RESTART_CLR reader - Reserved.
  • OUT_NO_RESTART_CLR_W
    Field OUT_NO_RESTART_CLR writer - Reserved.
  • OUT_RST_R
    Field OUT_RST reader - Set this bit to reset out DMA FSM.
  • OUT_RST_W
    Field OUT_RST writer - Set this bit to reset out DMA FSM.
  • R
    Register CONF0 reader
  • SEPER_EN_R
    Field SEPER_EN reader - Set this bit to separate the data frame using a special character.
  • SEPER_EN_W
    Field SEPER_EN writer - Set this bit to separate the data frame using a special character.
  • UART0_CE_R
    Field UART0_CE reader - Set this bit to link up UHCI and UART0.
  • UART0_CE_W
    Field UART0_CE writer - Set this bit to link up UHCI and UART0.
  • UART1_CE_R
    Field UART1_CE reader - Set this bit to link up UHCI and UART1.
  • UART1_CE_W
    Field UART1_CE writer - Set this bit to link up UHCI and UART1.
  • UART_IDLE_EOF_EN_R
    Field UART_IDLE_EOF_EN reader - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
  • UART_IDLE_EOF_EN_W
    Field UART_IDLE_EOF_EN writer - If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
  • UART_RX_BRK_EOF_EN_R
    Field UART_RX_BRK_EOF_EN reader - If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART.
  • UART_RX_BRK_EOF_EN_W
    Field UART_RX_BRK_EOF_EN writer - If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART.
  • W
    Register CONF0 writer