Module esp32s2::spi0::ctrl

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Expand description

SPI control register

Structs

Type Aliases

  • DUMMY_OUT_R
    Field DUMMY_OUT reader - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
  • DUMMY_OUT_W
    Field DUMMY_OUT writer - In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
  • D_POL_R
    Field D_POL reader - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
  • D_POL_W
    Field D_POL writer - The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
  • EXT_HOLD_EN_R
    Field EXT_HOLD_EN reader - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state.
  • EXT_HOLD_EN_W
    Field EXT_HOLD_EN writer - Set the bit to hold spi. The bit is combined with SPI_USR_PREP_HOLD,SPI_USR_CMD_HOLD,SPI_USR_ADDR_HOLD,SPI_USR_DUMMY_HOLD,SPI_USR_DIN_HOLD,SPI_USR_DOUT_HOLD and SPI_USR_HOLD_POL. Can be configured in CONF state.
  • FADDR_DUAL_R
    Field FADDR_DUAL reader - Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
  • FADDR_DUAL_W
    Field FADDR_DUAL writer - Apply 2-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
  • FADDR_OCT_R
    Field FADDR_OCT reader - Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
  • FADDR_OCT_W
    Field FADDR_OCT writer - Apply 8-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
  • FADDR_QUAD_R
    Field FADDR_QUAD reader - Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
  • FADDR_QUAD_W
    Field FADDR_QUAD writer - Apply 4-bit mode during addr phase 1:enable 0: disable. Can be configured in CONF state.
  • FCMD_DUAL_R
    Field FCMD_DUAL reader - Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
  • FCMD_DUAL_W
    Field FCMD_DUAL writer - Apply 2-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
  • FCMD_OCT_R
    Field FCMD_OCT reader - Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
  • FCMD_OCT_W
    Field FCMD_OCT writer - Apply 8-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
  • FCMD_QUAD_R
    Field FCMD_QUAD reader - Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
  • FCMD_QUAD_W
    Field FCMD_QUAD writer - Apply 4-bit mode during command phase 1:enable 0: disable. Can be configured in CONF state.
  • FREAD_DUAL_R
    Field FREAD_DUAL reader - In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state.
  • FREAD_DUAL_W
    Field FREAD_DUAL writer - In the read operations, read-data phase is in 2-bit mode. 1: enable 0: disable. Can be configured in CONF state.
  • FREAD_OCT_R
    Field FREAD_OCT reader - In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state.
  • FREAD_OCT_W
    Field FREAD_OCT writer - In the read operations read-data phase is in 8-bit mode. 1: enable 0: disable. Can be configured in CONF state.
  • FREAD_QUAD_R
    Field FREAD_QUAD reader - In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state.
  • FREAD_QUAD_W
    Field FREAD_QUAD writer - In the read operations read-data phase is in 4-bit mode. 1: enable 0: disable. Can be configured in CONF state.
  • Q_POL_R
    Field Q_POL reader - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
  • Q_POL_W
    Field Q_POL writer - The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
  • R
    Register CTRL reader
  • RD_BIT_ORDER_R
    Field RD_BIT_ORDER reader - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
  • RD_BIT_ORDER_W
    Field RD_BIT_ORDER writer - In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
  • W
    Register CTRL writer
  • WP_R
    Field WP reader - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
  • WP_W
    Field WP writer - Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
  • WR_BIT_ORDER_R
    Field WR_BIT_ORDER reader - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
  • WR_BIT_ORDER_W
    Field WR_BIT_ORDER writer - In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.