Module esp32s2::spi0::clock

SPI clock control register

Structs

• CLOCK_SPEC
  SPI clock control register

Type Aliases

• CLKCNT_H_R
  Field CLKCNT_H reader - In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
• CLKCNT_H_W
  Field CLKCNT_H writer - In the master mode it must be floor((SPI_CLKCNT_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
• CLKCNT_L_R
  Field CLKCNT_L reader - In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state.
• CLKCNT_L_W
  Field CLKCNT_L writer - In the master mode it must be equal to SPI_CLKCNT_N. In the slave mode it must be 0. Can be configured in CONF state.
• CLKCNT_N_R
  Field CLKCNT_N reader - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state.
• CLKCNT_N_W
  Field CLKCNT_N writer - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(SPI_CLKDIV_PRE+1)/(SPI_CLKCNT_N+1). Can be configured in CONF state.
• CLKDIV_PRE_R
  Field CLKDIV_PRE reader - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
• CLKDIV_PRE_W
  Field CLKDIV_PRE writer - In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
• CLK_EQU_SYSCLK_R
  Field CLK_EQU_SYSCLK reader - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
• CLK_EQU_SYSCLK_W
  Field CLK_EQU_SYSCLK writer - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
• R
  Register CLOCK reader
• W
  Register CLOCK writer