esp32s2_ulp/
sens.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    _reserved0: [u8; 0x40],
6    sar_slave_addr1: SAR_SLAVE_ADDR1,
7    sar_slave_addr2: SAR_SLAVE_ADDR2,
8    sar_slave_addr3: SAR_SLAVE_ADDR3,
9    sar_slave_addr4: SAR_SLAVE_ADDR4,
10    _reserved4: [u8; 0x08],
11    sar_i2c_ctrl: SAR_I2C_CTRL,
12    _reserved5: [u8; 0xcc],
13    sar_cocpu_int_raw: SAR_COCPU_INT_RAW,
14    sar_cocpu_int_ena: SAR_COCPU_INT_ENA,
15    sar_cocpu_int_st: SAR_COCPU_INT_ST,
16    sar_cocpu_int_clr: SAR_COCPU_INT_CLR,
17}
18impl RegisterBlock {
19    #[doc = "0x40 - Configure slave addresses 0-1 of RTC I2C"]
20    #[inline(always)]
21    pub const fn sar_slave_addr1(&self) -> &SAR_SLAVE_ADDR1 {
22        &self.sar_slave_addr1
23    }
24    #[doc = "0x44 - Configure slave addresses 2-3 of RTC I2C"]
25    #[inline(always)]
26    pub const fn sar_slave_addr2(&self) -> &SAR_SLAVE_ADDR2 {
27        &self.sar_slave_addr2
28    }
29    #[doc = "0x48 - Configure slave addresses 4-5 of RTC I2C"]
30    #[inline(always)]
31    pub const fn sar_slave_addr3(&self) -> &SAR_SLAVE_ADDR3 {
32        &self.sar_slave_addr3
33    }
34    #[doc = "0x4c - Configure slave addresses 6-7 of RTC I2C"]
35    #[inline(always)]
36    pub const fn sar_slave_addr4(&self) -> &SAR_SLAVE_ADDR4 {
37        &self.sar_slave_addr4
38    }
39    #[doc = "0x58 - Configure RTC I2C transmission"]
40    #[inline(always)]
41    pub const fn sar_i2c_ctrl(&self) -> &SAR_I2C_CTRL {
42        &self.sar_i2c_ctrl
43    }
44    #[doc = "0x128 - Interrupt raw bit of ULP-RISCV"]
45    #[inline(always)]
46    pub const fn sar_cocpu_int_raw(&self) -> &SAR_COCPU_INT_RAW {
47        &self.sar_cocpu_int_raw
48    }
49    #[doc = "0x12c - Interrupt enable bit of ULP-RISCV"]
50    #[inline(always)]
51    pub const fn sar_cocpu_int_ena(&self) -> &SAR_COCPU_INT_ENA {
52        &self.sar_cocpu_int_ena
53    }
54    #[doc = "0x130 - Interrupt status bit of ULP-RISCV"]
55    #[inline(always)]
56    pub const fn sar_cocpu_int_st(&self) -> &SAR_COCPU_INT_ST {
57        &self.sar_cocpu_int_st
58    }
59    #[doc = "0x134 - Interrupt clear bit of ULP-RISCV"]
60    #[inline(always)]
61    pub const fn sar_cocpu_int_clr(&self) -> &SAR_COCPU_INT_CLR {
62        &self.sar_cocpu_int_clr
63    }
64}
65#[doc = "SAR_SLAVE_ADDR1 (rw) register accessor: Configure slave addresses 0-1 of RTC I2C\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_slave_addr1`] module"]
66pub type SAR_SLAVE_ADDR1 = crate::Reg<sar_slave_addr1::SAR_SLAVE_ADDR1_SPEC>;
67#[doc = "Configure slave addresses 0-1 of RTC I2C"]
68pub mod sar_slave_addr1;
69#[doc = "SAR_SLAVE_ADDR2 (rw) register accessor: Configure slave addresses 2-3 of RTC I2C\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_slave_addr2`] module"]
70pub type SAR_SLAVE_ADDR2 = crate::Reg<sar_slave_addr2::SAR_SLAVE_ADDR2_SPEC>;
71#[doc = "Configure slave addresses 2-3 of RTC I2C"]
72pub mod sar_slave_addr2;
73#[doc = "SAR_SLAVE_ADDR3 (rw) register accessor: Configure slave addresses 4-5 of RTC I2C\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_slave_addr3`] module"]
74pub type SAR_SLAVE_ADDR3 = crate::Reg<sar_slave_addr3::SAR_SLAVE_ADDR3_SPEC>;
75#[doc = "Configure slave addresses 4-5 of RTC I2C"]
76pub mod sar_slave_addr3;
77#[doc = "SAR_SLAVE_ADDR4 (rw) register accessor: Configure slave addresses 6-7 of RTC I2C\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_slave_addr4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_slave_addr4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_slave_addr4`] module"]
78pub type SAR_SLAVE_ADDR4 = crate::Reg<sar_slave_addr4::SAR_SLAVE_ADDR4_SPEC>;
79#[doc = "Configure slave addresses 6-7 of RTC I2C"]
80pub mod sar_slave_addr4;
81#[doc = "SAR_I2C_CTRL (rw) register accessor: Configure RTC I2C transmission\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_i2c_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_i2c_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_i2c_ctrl`] module"]
82pub type SAR_I2C_CTRL = crate::Reg<sar_i2c_ctrl::SAR_I2C_CTRL_SPEC>;
83#[doc = "Configure RTC I2C transmission"]
84pub mod sar_i2c_ctrl;
85#[doc = "SAR_COCPU_INT_RAW (r) register accessor: Interrupt raw bit of ULP-RISCV\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_raw::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_cocpu_int_raw`] module"]
86pub type SAR_COCPU_INT_RAW = crate::Reg<sar_cocpu_int_raw::SAR_COCPU_INT_RAW_SPEC>;
87#[doc = "Interrupt raw bit of ULP-RISCV"]
88pub mod sar_cocpu_int_raw;
89#[doc = "SAR_COCPU_INT_ENA (rw) register accessor: Interrupt enable bit of ULP-RISCV\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_ena::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_ena::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_cocpu_int_ena`] module"]
90pub type SAR_COCPU_INT_ENA = crate::Reg<sar_cocpu_int_ena::SAR_COCPU_INT_ENA_SPEC>;
91#[doc = "Interrupt enable bit of ULP-RISCV"]
92pub mod sar_cocpu_int_ena;
93#[doc = "SAR_COCPU_INT_ST (r) register accessor: Interrupt status bit of ULP-RISCV\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_st::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_cocpu_int_st`] module"]
94pub type SAR_COCPU_INT_ST = crate::Reg<sar_cocpu_int_st::SAR_COCPU_INT_ST_SPEC>;
95#[doc = "Interrupt status bit of ULP-RISCV"]
96pub mod sar_cocpu_int_st;
97#[doc = "SAR_COCPU_INT_CLR (w) register accessor: Interrupt clear bit of ULP-RISCV\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_clr::W`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@sar_cocpu_int_clr`] module"]
98pub type SAR_COCPU_INT_CLR = crate::Reg<sar_cocpu_int_clr::SAR_COCPU_INT_CLR_SPEC>;
99#[doc = "Interrupt clear bit of ULP-RISCV"]
100pub mod sar_cocpu_int_clr;