esp32s2_ulp/sens/
sar_cocpu_int_ena.rs

1#[doc = "Register `SAR_COCPU_INT_ENA` reader"]
2pub type R = crate::R<SAR_COCPU_INT_ENA_SPEC>;
3#[doc = "Register `SAR_COCPU_INT_ENA` writer"]
4pub type W = crate::W<SAR_COCPU_INT_ENA_SPEC>;
5#[doc = "Field `COCPU_TOUCH_DONE_INT_ENA` reader - TOUCH_DONE_INT interrupt enable bit"]
6pub type COCPU_TOUCH_DONE_INT_ENA_R = crate::BitReader;
7#[doc = "Field `COCPU_TOUCH_DONE_INT_ENA` writer - TOUCH_DONE_INT interrupt enable bit"]
8pub type COCPU_TOUCH_DONE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `COCPU_TOUCH_INACTIVE_INT_ENA` reader - TOUCH_INACTIVE_INT interrupt enable bit"]
10pub type COCPU_TOUCH_INACTIVE_INT_ENA_R = crate::BitReader;
11#[doc = "Field `COCPU_TOUCH_INACTIVE_INT_ENA` writer - TOUCH_INACTIVE_INT interrupt enable bit"]
12pub type COCPU_TOUCH_INACTIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `COCPU_TOUCH_ACTIVE_INT_ENA` reader - TOUCH_ACTIVE_INT interrupt enable bit"]
14pub type COCPU_TOUCH_ACTIVE_INT_ENA_R = crate::BitReader;
15#[doc = "Field `COCPU_TOUCH_ACTIVE_INT_ENA` writer - TOUCH_ACTIVE_INT interrupt enable bit"]
16pub type COCPU_TOUCH_ACTIVE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `COCPU_SARADC1_INT_ENA` reader - SARADC1_DONE_INT interrupt enable bit"]
18pub type COCPU_SARADC1_INT_ENA_R = crate::BitReader;
19#[doc = "Field `COCPU_SARADC1_INT_ENA` writer - SARADC1_DONE_INT interrupt enable bit"]
20pub type COCPU_SARADC1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `COCPU_SARADC2_INT_ENA` reader - SARADC2_DONE_INT interrupt enable bit"]
22pub type COCPU_SARADC2_INT_ENA_R = crate::BitReader;
23#[doc = "Field `COCPU_SARADC2_INT_ENA` writer - SARADC2_DONE_INT interrupt enable bit"]
24pub type COCPU_SARADC2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `COCPU_TSENS_INT_ENA` reader - TSENS_DONE_INT interrupt enable bit"]
26pub type COCPU_TSENS_INT_ENA_R = crate::BitReader;
27#[doc = "Field `COCPU_TSENS_INT_ENA` writer - TSENS_DONE_INT interrupt enable bit"]
28pub type COCPU_TSENS_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `COCPU_START_INT_ENA` reader - RISCV_START_INT interrupt enable bit"]
30pub type COCPU_START_INT_ENA_R = crate::BitReader;
31#[doc = "Field `COCPU_START_INT_ENA` writer - RISCV_START_INT interrupt enable bit"]
32pub type COCPU_START_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `COCPU_SW_INT_ENA` reader - SW_INT interrupt enable bit"]
34pub type COCPU_SW_INT_ENA_R = crate::BitReader;
35#[doc = "Field `COCPU_SW_INT_ENA` writer - SW_INT interrupt enable bit"]
36pub type COCPU_SW_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `COCPU_SWD_INT_ENA` reader - SWD_INT interrupt enable bit"]
38pub type COCPU_SWD_INT_ENA_R = crate::BitReader;
39#[doc = "Field `COCPU_SWD_INT_ENA` writer - SWD_INT interrupt enable bit"]
40pub type COCPU_SWD_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
41impl R {
42    #[doc = "Bit 0 - TOUCH_DONE_INT interrupt enable bit"]
43    #[inline(always)]
44    pub fn cocpu_touch_done_int_ena(&self) -> COCPU_TOUCH_DONE_INT_ENA_R {
45        COCPU_TOUCH_DONE_INT_ENA_R::new((self.bits & 1) != 0)
46    }
47    #[doc = "Bit 1 - TOUCH_INACTIVE_INT interrupt enable bit"]
48    #[inline(always)]
49    pub fn cocpu_touch_inactive_int_ena(&self) -> COCPU_TOUCH_INACTIVE_INT_ENA_R {
50        COCPU_TOUCH_INACTIVE_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
51    }
52    #[doc = "Bit 2 - TOUCH_ACTIVE_INT interrupt enable bit"]
53    #[inline(always)]
54    pub fn cocpu_touch_active_int_ena(&self) -> COCPU_TOUCH_ACTIVE_INT_ENA_R {
55        COCPU_TOUCH_ACTIVE_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
56    }
57    #[doc = "Bit 3 - SARADC1_DONE_INT interrupt enable bit"]
58    #[inline(always)]
59    pub fn cocpu_saradc1_int_ena(&self) -> COCPU_SARADC1_INT_ENA_R {
60        COCPU_SARADC1_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
61    }
62    #[doc = "Bit 4 - SARADC2_DONE_INT interrupt enable bit"]
63    #[inline(always)]
64    pub fn cocpu_saradc2_int_ena(&self) -> COCPU_SARADC2_INT_ENA_R {
65        COCPU_SARADC2_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
66    }
67    #[doc = "Bit 5 - TSENS_DONE_INT interrupt enable bit"]
68    #[inline(always)]
69    pub fn cocpu_tsens_int_ena(&self) -> COCPU_TSENS_INT_ENA_R {
70        COCPU_TSENS_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
71    }
72    #[doc = "Bit 6 - RISCV_START_INT interrupt enable bit"]
73    #[inline(always)]
74    pub fn cocpu_start_int_ena(&self) -> COCPU_START_INT_ENA_R {
75        COCPU_START_INT_ENA_R::new(((self.bits >> 6) & 1) != 0)
76    }
77    #[doc = "Bit 7 - SW_INT interrupt enable bit"]
78    #[inline(always)]
79    pub fn cocpu_sw_int_ena(&self) -> COCPU_SW_INT_ENA_R {
80        COCPU_SW_INT_ENA_R::new(((self.bits >> 7) & 1) != 0)
81    }
82    #[doc = "Bit 8 - SWD_INT interrupt enable bit"]
83    #[inline(always)]
84    pub fn cocpu_swd_int_ena(&self) -> COCPU_SWD_INT_ENA_R {
85        COCPU_SWD_INT_ENA_R::new(((self.bits >> 8) & 1) != 0)
86    }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91        f.debug_struct("SAR_COCPU_INT_ENA")
92            .field("cocpu_touch_done_int_ena", &self.cocpu_touch_done_int_ena())
93            .field(
94                "cocpu_touch_inactive_int_ena",
95                &self.cocpu_touch_inactive_int_ena(),
96            )
97            .field(
98                "cocpu_touch_active_int_ena",
99                &self.cocpu_touch_active_int_ena(),
100            )
101            .field("cocpu_saradc1_int_ena", &self.cocpu_saradc1_int_ena())
102            .field("cocpu_saradc2_int_ena", &self.cocpu_saradc2_int_ena())
103            .field("cocpu_tsens_int_ena", &self.cocpu_tsens_int_ena())
104            .field("cocpu_start_int_ena", &self.cocpu_start_int_ena())
105            .field("cocpu_sw_int_ena", &self.cocpu_sw_int_ena())
106            .field("cocpu_swd_int_ena", &self.cocpu_swd_int_ena())
107            .finish()
108    }
109}
110impl W {
111    #[doc = "Bit 0 - TOUCH_DONE_INT interrupt enable bit"]
112    #[inline(always)]
113    #[must_use]
114    pub fn cocpu_touch_done_int_ena(
115        &mut self,
116    ) -> COCPU_TOUCH_DONE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
117        COCPU_TOUCH_DONE_INT_ENA_W::new(self, 0)
118    }
119    #[doc = "Bit 1 - TOUCH_INACTIVE_INT interrupt enable bit"]
120    #[inline(always)]
121    #[must_use]
122    pub fn cocpu_touch_inactive_int_ena(
123        &mut self,
124    ) -> COCPU_TOUCH_INACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
125        COCPU_TOUCH_INACTIVE_INT_ENA_W::new(self, 1)
126    }
127    #[doc = "Bit 2 - TOUCH_ACTIVE_INT interrupt enable bit"]
128    #[inline(always)]
129    #[must_use]
130    pub fn cocpu_touch_active_int_ena(
131        &mut self,
132    ) -> COCPU_TOUCH_ACTIVE_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
133        COCPU_TOUCH_ACTIVE_INT_ENA_W::new(self, 2)
134    }
135    #[doc = "Bit 3 - SARADC1_DONE_INT interrupt enable bit"]
136    #[inline(always)]
137    #[must_use]
138    pub fn cocpu_saradc1_int_ena(&mut self) -> COCPU_SARADC1_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
139        COCPU_SARADC1_INT_ENA_W::new(self, 3)
140    }
141    #[doc = "Bit 4 - SARADC2_DONE_INT interrupt enable bit"]
142    #[inline(always)]
143    #[must_use]
144    pub fn cocpu_saradc2_int_ena(&mut self) -> COCPU_SARADC2_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
145        COCPU_SARADC2_INT_ENA_W::new(self, 4)
146    }
147    #[doc = "Bit 5 - TSENS_DONE_INT interrupt enable bit"]
148    #[inline(always)]
149    #[must_use]
150    pub fn cocpu_tsens_int_ena(&mut self) -> COCPU_TSENS_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
151        COCPU_TSENS_INT_ENA_W::new(self, 5)
152    }
153    #[doc = "Bit 6 - RISCV_START_INT interrupt enable bit"]
154    #[inline(always)]
155    #[must_use]
156    pub fn cocpu_start_int_ena(&mut self) -> COCPU_START_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
157        COCPU_START_INT_ENA_W::new(self, 6)
158    }
159    #[doc = "Bit 7 - SW_INT interrupt enable bit"]
160    #[inline(always)]
161    #[must_use]
162    pub fn cocpu_sw_int_ena(&mut self) -> COCPU_SW_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
163        COCPU_SW_INT_ENA_W::new(self, 7)
164    }
165    #[doc = "Bit 8 - SWD_INT interrupt enable bit"]
166    #[inline(always)]
167    #[must_use]
168    pub fn cocpu_swd_int_ena(&mut self) -> COCPU_SWD_INT_ENA_W<SAR_COCPU_INT_ENA_SPEC> {
169        COCPU_SWD_INT_ENA_W::new(self, 8)
170    }
171}
172#[doc = "Interrupt enable bit of ULP-RISCV\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_ena::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_ena::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
173pub struct SAR_COCPU_INT_ENA_SPEC;
174impl crate::RegisterSpec for SAR_COCPU_INT_ENA_SPEC {
175    type Ux = u32;
176}
177#[doc = "`read()` method returns [`sar_cocpu_int_ena::R`](R) reader structure"]
178impl crate::Readable for SAR_COCPU_INT_ENA_SPEC {}
179#[doc = "`write(|w| ..)` method takes [`sar_cocpu_int_ena::W`](W) writer structure"]
180impl crate::Writable for SAR_COCPU_INT_ENA_SPEC {
181    type Safety = crate::Unsafe;
182    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
183    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
184}
185#[doc = "`reset()` method sets SAR_COCPU_INT_ENA to value 0"]
186impl crate::Resettable for SAR_COCPU_INT_ENA_SPEC {
187    const RESET_VALUE: u32 = 0;
188}
esp32s2_ulp/sens/sar_cocpu_int_ena.rs

esp32s2_ulp/sens/
sar_cocpu_int_ena.rs
