esp32s2_ulp/rtc_cntl/
cocpu_ctrl.rs

1#[doc = "Register `COCPU_CTRL` reader"]
2pub type R = crate::R<COCPU_CTRL_SPEC>;
3#[doc = "Register `COCPU_CTRL` writer"]
4pub type W = crate::W<COCPU_CTRL_SPEC>;
5#[doc = "Field `COCPU_CLK_FO` reader - ULP-RISCV clock force on"]
6pub type COCPU_CLK_FO_R = crate::BitReader;
7#[doc = "Field `COCPU_CLK_FO` writer - ULP-RISCV clock force on"]
8pub type COCPU_CLK_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `COCPU_START_2_RESET_DIS` reader - Time from ULP-RISCV startup to pull down reset"]
10pub type COCPU_START_2_RESET_DIS_R = crate::FieldReader;
11#[doc = "Field `COCPU_START_2_RESET_DIS` writer - Time from ULP-RISCV startup to pull down reset"]
12pub type COCPU_START_2_RESET_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13#[doc = "Field `COCPU_START_2_INTR_EN` reader - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt"]
14pub type COCPU_START_2_INTR_EN_R = crate::FieldReader;
15#[doc = "Field `COCPU_START_2_INTR_EN` writer - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt"]
16pub type COCPU_START_2_INTR_EN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
17#[doc = "Field `COCPU_SHUT` reader - Shut down ULP-RISCV"]
18pub type COCPU_SHUT_R = crate::BitReader;
19#[doc = "Field `COCPU_SHUT` writer - Shut down ULP-RISCV"]
20pub type COCPU_SHUT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `COCPU_SHUT_2_CLK_DIS` reader - Time from shut down ULP-RISCV to disable clock"]
22pub type COCPU_SHUT_2_CLK_DIS_R = crate::FieldReader;
23#[doc = "Field `COCPU_SHUT_2_CLK_DIS` writer - Time from shut down ULP-RISCV to disable clock"]
24pub type COCPU_SHUT_2_CLK_DIS_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
25#[doc = "Field `COCPU_SHUT_RESET_EN` reader - This bit is used to reset ULP-RISCV"]
26pub type COCPU_SHUT_RESET_EN_R = crate::BitReader;
27#[doc = "Field `COCPU_SHUT_RESET_EN` writer - This bit is used to reset ULP-RISCV"]
28pub type COCPU_SHUT_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `COCPU_SEL` reader - 0: select ULP-RISCV. 1: select ULP-FSM"]
30pub type COCPU_SEL_R = crate::BitReader;
31#[doc = "Field `COCPU_SEL` writer - 0: select ULP-RISCV. 1: select ULP-FSM"]
32pub type COCPU_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `COCPU_DONE_FORCE` reader - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal"]
34pub type COCPU_DONE_FORCE_R = crate::BitReader;
35#[doc = "Field `COCPU_DONE_FORCE` writer - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal"]
36pub type COCPU_DONE_FORCE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `COCPU_DONE` reader - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting"]
38pub type COCPU_DONE_R = crate::BitReader;
39#[doc = "Field `COCPU_DONE` writer - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting"]
40pub type COCPU_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `COCPU_SW_INT_TRIGGER` writer - Trigger ULP-RISCV register interrupt"]
42pub type COCPU_SW_INT_TRIGGER_W<'a, REG> = crate::BitWriter<'a, REG>;
43impl R {
44    #[doc = "Bit 0 - ULP-RISCV clock force on"]
45    #[inline(always)]
46    pub fn cocpu_clk_fo(&self) -> COCPU_CLK_FO_R {
47        COCPU_CLK_FO_R::new((self.bits & 1) != 0)
48    }
49    #[doc = "Bits 1:6 - Time from ULP-RISCV startup to pull down reset"]
50    #[inline(always)]
51    pub fn cocpu_start_2_reset_dis(&self) -> COCPU_START_2_RESET_DIS_R {
52        COCPU_START_2_RESET_DIS_R::new(((self.bits >> 1) & 0x3f) as u8)
53    }
54    #[doc = "Bits 7:12 - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt"]
55    #[inline(always)]
56    pub fn cocpu_start_2_intr_en(&self) -> COCPU_START_2_INTR_EN_R {
57        COCPU_START_2_INTR_EN_R::new(((self.bits >> 7) & 0x3f) as u8)
58    }
59    #[doc = "Bit 13 - Shut down ULP-RISCV"]
60    #[inline(always)]
61    pub fn cocpu_shut(&self) -> COCPU_SHUT_R {
62        COCPU_SHUT_R::new(((self.bits >> 13) & 1) != 0)
63    }
64    #[doc = "Bits 14:21 - Time from shut down ULP-RISCV to disable clock"]
65    #[inline(always)]
66    pub fn cocpu_shut_2_clk_dis(&self) -> COCPU_SHUT_2_CLK_DIS_R {
67        COCPU_SHUT_2_CLK_DIS_R::new(((self.bits >> 14) & 0xff) as u8)
68    }
69    #[doc = "Bit 22 - This bit is used to reset ULP-RISCV"]
70    #[inline(always)]
71    pub fn cocpu_shut_reset_en(&self) -> COCPU_SHUT_RESET_EN_R {
72        COCPU_SHUT_RESET_EN_R::new(((self.bits >> 22) & 1) != 0)
73    }
74    #[doc = "Bit 23 - 0: select ULP-RISCV. 1: select ULP-FSM"]
75    #[inline(always)]
76    pub fn cocpu_sel(&self) -> COCPU_SEL_R {
77        COCPU_SEL_R::new(((self.bits >> 23) & 1) != 0)
78    }
79    #[doc = "Bit 24 - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal"]
80    #[inline(always)]
81    pub fn cocpu_done_force(&self) -> COCPU_DONE_FORCE_R {
82        COCPU_DONE_FORCE_R::new(((self.bits >> 24) & 1) != 0)
83    }
84    #[doc = "Bit 25 - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting"]
85    #[inline(always)]
86    pub fn cocpu_done(&self) -> COCPU_DONE_R {
87        COCPU_DONE_R::new(((self.bits >> 25) & 1) != 0)
88    }
89}
90#[cfg(feature = "impl-register-debug")]
91impl core::fmt::Debug for R {
92    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
93        f.debug_struct("COCPU_CTRL")
94            .field("cocpu_clk_fo", &self.cocpu_clk_fo())
95            .field("cocpu_start_2_reset_dis", &self.cocpu_start_2_reset_dis())
96            .field("cocpu_start_2_intr_en", &self.cocpu_start_2_intr_en())
97            .field("cocpu_shut", &self.cocpu_shut())
98            .field("cocpu_shut_2_clk_dis", &self.cocpu_shut_2_clk_dis())
99            .field("cocpu_shut_reset_en", &self.cocpu_shut_reset_en())
100            .field("cocpu_sel", &self.cocpu_sel())
101            .field("cocpu_done_force", &self.cocpu_done_force())
102            .field("cocpu_done", &self.cocpu_done())
103            .finish()
104    }
105}
106impl W {
107    #[doc = "Bit 0 - ULP-RISCV clock force on"]
108    #[inline(always)]
109    #[must_use]
110    pub fn cocpu_clk_fo(&mut self) -> COCPU_CLK_FO_W<COCPU_CTRL_SPEC> {
111        COCPU_CLK_FO_W::new(self, 0)
112    }
113    #[doc = "Bits 1:6 - Time from ULP-RISCV startup to pull down reset"]
114    #[inline(always)]
115    #[must_use]
116    pub fn cocpu_start_2_reset_dis(&mut self) -> COCPU_START_2_RESET_DIS_W<COCPU_CTRL_SPEC> {
117        COCPU_START_2_RESET_DIS_W::new(self, 1)
118    }
119    #[doc = "Bits 7:12 - Time from ULP-RISCV startup to send out RISCV_START_INT interrupt"]
120    #[inline(always)]
121    #[must_use]
122    pub fn cocpu_start_2_intr_en(&mut self) -> COCPU_START_2_INTR_EN_W<COCPU_CTRL_SPEC> {
123        COCPU_START_2_INTR_EN_W::new(self, 7)
124    }
125    #[doc = "Bit 13 - Shut down ULP-RISCV"]
126    #[inline(always)]
127    #[must_use]
128    pub fn cocpu_shut(&mut self) -> COCPU_SHUT_W<COCPU_CTRL_SPEC> {
129        COCPU_SHUT_W::new(self, 13)
130    }
131    #[doc = "Bits 14:21 - Time from shut down ULP-RISCV to disable clock"]
132    #[inline(always)]
133    #[must_use]
134    pub fn cocpu_shut_2_clk_dis(&mut self) -> COCPU_SHUT_2_CLK_DIS_W<COCPU_CTRL_SPEC> {
135        COCPU_SHUT_2_CLK_DIS_W::new(self, 14)
136    }
137    #[doc = "Bit 22 - This bit is used to reset ULP-RISCV"]
138    #[inline(always)]
139    #[must_use]
140    pub fn cocpu_shut_reset_en(&mut self) -> COCPU_SHUT_RESET_EN_W<COCPU_CTRL_SPEC> {
141        COCPU_SHUT_RESET_EN_W::new(self, 22)
142    }
143    #[doc = "Bit 23 - 0: select ULP-RISCV. 1: select ULP-FSM"]
144    #[inline(always)]
145    #[must_use]
146    pub fn cocpu_sel(&mut self) -> COCPU_SEL_W<COCPU_CTRL_SPEC> {
147        COCPU_SEL_W::new(self, 23)
148    }
149    #[doc = "Bit 24 - 0: select ULP-FSM DONE signal. 1: select ULP-RISCV DONE signal"]
150    #[inline(always)]
151    #[must_use]
152    pub fn cocpu_done_force(&mut self) -> COCPU_DONE_FORCE_W<COCPU_CTRL_SPEC> {
153        COCPU_DONE_FORCE_W::new(self, 24)
154    }
155    #[doc = "Bit 25 - DONE signal. Write 1 to this bit, ULP-RISCV will go to HALT and the timer starts counting"]
156    #[inline(always)]
157    #[must_use]
158    pub fn cocpu_done(&mut self) -> COCPU_DONE_W<COCPU_CTRL_SPEC> {
159        COCPU_DONE_W::new(self, 25)
160    }
161    #[doc = "Bit 26 - Trigger ULP-RISCV register interrupt"]
162    #[inline(always)]
163    #[must_use]
164    pub fn cocpu_sw_int_trigger(&mut self) -> COCPU_SW_INT_TRIGGER_W<COCPU_CTRL_SPEC> {
165        COCPU_SW_INT_TRIGGER_W::new(self, 26)
166    }
167}
168#[doc = "ULP-RISCV configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cocpu_ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cocpu_ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
169pub struct COCPU_CTRL_SPEC;
170impl crate::RegisterSpec for COCPU_CTRL_SPEC {
171    type Ux = u32;
172}
173#[doc = "`read()` method returns [`cocpu_ctrl::R`](R) reader structure"]
174impl crate::Readable for COCPU_CTRL_SPEC {}
175#[doc = "`write(|w| ..)` method takes [`cocpu_ctrl::W`](W) writer structure"]
176impl crate::Writable for COCPU_CTRL_SPEC {
177    type Safety = crate::Unsafe;
178    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
179    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
180}
181#[doc = "`reset()` method sets COCPU_CTRL to value 0x008a_0810"]
182impl crate::Resettable for COCPU_CTRL_SPEC {
183    const RESET_VALUE: u32 = 0x008a_0810;
184}
esp32s2_ulp/rtc_cntl/cocpu_ctrl.rs

esp32s2_ulp/rtc_cntl/
cocpu_ctrl.rs
