esp32s2_ulp/sens/
sar_cocpu_int_clr.rs

1#[doc = "Register `SAR_COCPU_INT_CLR` writer"]
2pub type W = crate::W<SAR_COCPU_INT_CLR_SPEC>;
3#[doc = "Field `COCPU_TOUCH_DONE_INT_CLR` writer - TOUCH_DONE_INT interrupt clear bit"]
4pub type COCPU_TOUCH_DONE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
5#[doc = "Field `COCPU_TOUCH_INACTIVE_INT_CLR` writer - TOUCH_INACTIVE_INT interrupt clear bit"]
6pub type COCPU_TOUCH_INACTIVE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `COCPU_TOUCH_ACTIVE_INT_CLR` writer - TOUCH_ACTIVE_INT interrupt clear bit"]
8pub type COCPU_TOUCH_ACTIVE_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `COCPU_SARADC1_INT_CLR` writer - SARADC1_DONE_INT interrupt clear bit"]
10pub type COCPU_SARADC1_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
11#[doc = "Field `COCPU_SARADC2_INT_CLR` writer - SARADC2_DONE_INT interrupt clear bit"]
12pub type COCPU_SARADC2_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `COCPU_TSENS_INT_CLR` writer - TSENS_DONE_INT interrupt clear bit"]
14pub type COCPU_TSENS_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
15#[doc = "Field `COCPU_START_INT_CLR` writer - RISCV_START_INT interrupt clear bit"]
16pub type COCPU_START_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `COCPU_SW_INT_CLR` writer - SW_INT interrupt clear bit"]
18pub type COCPU_SW_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
19#[doc = "Field `COCPU_SWD_INT_CLR` writer - SWD_INT interrupt clear bit"]
20pub type COCPU_SWD_INT_CLR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[cfg(feature = "impl-register-debug")]
22impl core::fmt::Debug for crate::generic::Reg<SAR_COCPU_INT_CLR_SPEC> {
23    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24        write!(f, "(not readable)")
25    }
26}
27impl W {
28    #[doc = "Bit 0 - TOUCH_DONE_INT interrupt clear bit"]
29    #[inline(always)]
30    #[must_use]
31    pub fn cocpu_touch_done_int_clr(
32        &mut self,
33    ) -> COCPU_TOUCH_DONE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
34        COCPU_TOUCH_DONE_INT_CLR_W::new(self, 0)
35    }
36    #[doc = "Bit 1 - TOUCH_INACTIVE_INT interrupt clear bit"]
37    #[inline(always)]
38    #[must_use]
39    pub fn cocpu_touch_inactive_int_clr(
40        &mut self,
41    ) -> COCPU_TOUCH_INACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
42        COCPU_TOUCH_INACTIVE_INT_CLR_W::new(self, 1)
43    }
44    #[doc = "Bit 2 - TOUCH_ACTIVE_INT interrupt clear bit"]
45    #[inline(always)]
46    #[must_use]
47    pub fn cocpu_touch_active_int_clr(
48        &mut self,
49    ) -> COCPU_TOUCH_ACTIVE_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
50        COCPU_TOUCH_ACTIVE_INT_CLR_W::new(self, 2)
51    }
52    #[doc = "Bit 3 - SARADC1_DONE_INT interrupt clear bit"]
53    #[inline(always)]
54    #[must_use]
55    pub fn cocpu_saradc1_int_clr(&mut self) -> COCPU_SARADC1_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
56        COCPU_SARADC1_INT_CLR_W::new(self, 3)
57    }
58    #[doc = "Bit 4 - SARADC2_DONE_INT interrupt clear bit"]
59    #[inline(always)]
60    #[must_use]
61    pub fn cocpu_saradc2_int_clr(&mut self) -> COCPU_SARADC2_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
62        COCPU_SARADC2_INT_CLR_W::new(self, 4)
63    }
64    #[doc = "Bit 5 - TSENS_DONE_INT interrupt clear bit"]
65    #[inline(always)]
66    #[must_use]
67    pub fn cocpu_tsens_int_clr(&mut self) -> COCPU_TSENS_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
68        COCPU_TSENS_INT_CLR_W::new(self, 5)
69    }
70    #[doc = "Bit 6 - RISCV_START_INT interrupt clear bit"]
71    #[inline(always)]
72    #[must_use]
73    pub fn cocpu_start_int_clr(&mut self) -> COCPU_START_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
74        COCPU_START_INT_CLR_W::new(self, 6)
75    }
76    #[doc = "Bit 7 - SW_INT interrupt clear bit"]
77    #[inline(always)]
78    #[must_use]
79    pub fn cocpu_sw_int_clr(&mut self) -> COCPU_SW_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
80        COCPU_SW_INT_CLR_W::new(self, 7)
81    }
82    #[doc = "Bit 8 - SWD_INT interrupt clear bit"]
83    #[inline(always)]
84    #[must_use]
85    pub fn cocpu_swd_int_clr(&mut self) -> COCPU_SWD_INT_CLR_W<SAR_COCPU_INT_CLR_SPEC> {
86        COCPU_SWD_INT_CLR_W::new(self, 8)
87    }
88}
89#[doc = "Interrupt clear bit of ULP-RISCV\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`sar_cocpu_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
90pub struct SAR_COCPU_INT_CLR_SPEC;
91impl crate::RegisterSpec for SAR_COCPU_INT_CLR_SPEC {
92    type Ux = u32;
93}
94#[doc = "`write(|w| ..)` method takes [`sar_cocpu_int_clr::W`](W) writer structure"]
95impl crate::Writable for SAR_COCPU_INT_CLR_SPEC {
96    type Safety = crate::Unsafe;
97    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
98    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
99}
100#[doc = "`reset()` method sets SAR_COCPU_INT_CLR to value 0"]
101impl crate::Resettable for SAR_COCPU_INT_CLR_SPEC {
102    const RESET_VALUE: u32 = 0;
103}
esp32s2_ulp/sens/sar_cocpu_int_clr.rs

esp32s2_ulp/sens/
sar_cocpu_int_clr.rs
