esp32s2_ulp/
rtc_cntl.rs

1#[repr(C)]
2#[cfg_attr(feature = "impl-register-debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    _reserved0: [u8; 0xf8],
6    ulp_cp_timer: ULP_CP_TIMER,
7    ulp_cp_ctrl: ULP_CP_CTRL,
8    cocpu_ctrl: COCPU_CTRL,
9    _reserved3: [u8; 0x2c],
10    ulp_cp_timer_1: ULP_CP_TIMER_1,
11}
12impl RegisterBlock {
13    #[doc = "0xf8 - Configure coprocessor timer"]
14    #[inline(always)]
15    pub const fn ulp_cp_timer(&self) -> &ULP_CP_TIMER {
16        &self.ulp_cp_timer
17    }
18    #[doc = "0xfc - ULP-FSM configuration register"]
19    #[inline(always)]
20    pub const fn ulp_cp_ctrl(&self) -> &ULP_CP_CTRL {
21        &self.ulp_cp_ctrl
22    }
23    #[doc = "0x100 - ULP-RISCV configuration register"]
24    #[inline(always)]
25    pub const fn cocpu_ctrl(&self) -> &COCPU_CTRL {
26        &self.cocpu_ctrl
27    }
28    #[doc = "0x130 - Configure sleep cycle of the timer"]
29    #[inline(always)]
30    pub const fn ulp_cp_timer_1(&self) -> &ULP_CP_TIMER_1 {
31        &self.ulp_cp_timer_1
32    }
33}
34#[doc = "ULP_CP_TIMER (rw) register accessor: Configure coprocessor timer\n\nYou can [`read`](crate::Reg::read) this register and get [`ulp_cp_timer::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ulp_cp_timer::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ulp_cp_timer`] module"]
35pub type ULP_CP_TIMER = crate::Reg<ulp_cp_timer::ULP_CP_TIMER_SPEC>;
36#[doc = "Configure coprocessor timer"]
37pub mod ulp_cp_timer;
38#[doc = "ULP_CP_CTRL (rw) register accessor: ULP-FSM configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`ulp_cp_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ulp_cp_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ulp_cp_ctrl`] module"]
39pub type ULP_CP_CTRL = crate::Reg<ulp_cp_ctrl::ULP_CP_CTRL_SPEC>;
40#[doc = "ULP-FSM configuration register"]
41pub mod ulp_cp_ctrl;
42#[doc = "COCPU_CTRL (rw) register accessor: ULP-RISCV configuration register\n\nYou can [`read`](crate::Reg::read) this register and get [`cocpu_ctrl::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`cocpu_ctrl::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cocpu_ctrl`] module"]
43pub type COCPU_CTRL = crate::Reg<cocpu_ctrl::COCPU_CTRL_SPEC>;
44#[doc = "ULP-RISCV configuration register"]
45pub mod cocpu_ctrl;
46#[doc = "ULP_CP_TIMER_1 (rw) register accessor: Configure sleep cycle of the timer\n\nYou can [`read`](crate::Reg::read) this register and get [`ulp_cp_timer_1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ulp_cp_timer_1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ulp_cp_timer_1`] module"]
47pub type ULP_CP_TIMER_1 = crate::Reg<ulp_cp_timer_1::ULP_CP_TIMER_1_SPEC>;
48#[doc = "Configure sleep cycle of the timer"]
49pub mod ulp_cp_timer_1;
esp32s2_ulp/rtc_cntl.rs

esp32s2_ulp/
rtc_cntl.rs
