esp32s2_ulp/sens/
sar_cocpu_int_raw.rs

1#[doc = "Register `SAR_COCPU_INT_RAW` reader"]
2pub type R = crate::R<SAR_COCPU_INT_RAW_SPEC>;
3#[doc = "Field `COCPU_TOUCH_DONE_INT_RAW` reader - TOUCH_DONE_INT interrupt raw bit"]
4pub type COCPU_TOUCH_DONE_INT_RAW_R = crate::BitReader;
5#[doc = "Field `COCPU_TOUCH_INACTIVE_INT_RAW` reader - TOUCH_INACTIVE_INT interrupt raw bit"]
6pub type COCPU_TOUCH_INACTIVE_INT_RAW_R = crate::BitReader;
7#[doc = "Field `COCPU_TOUCH_ACTIVE_INT_RAW` reader - TOUCH_ACTIVE_INT interrupt raw bit"]
8pub type COCPU_TOUCH_ACTIVE_INT_RAW_R = crate::BitReader;
9#[doc = "Field `COCPU_SARADC1_INT_RAW` reader - SARADC1_DONE_INT interrupt raw bit"]
10pub type COCPU_SARADC1_INT_RAW_R = crate::BitReader;
11#[doc = "Field `COCPU_SARADC2_INT_RAW` reader - SARADC2_DONE_INT interrupt raw bit"]
12pub type COCPU_SARADC2_INT_RAW_R = crate::BitReader;
13#[doc = "Field `COCPU_TSENS_INT_RAW` reader - TSENS_DONE_INT interrupt raw bit"]
14pub type COCPU_TSENS_INT_RAW_R = crate::BitReader;
15#[doc = "Field `COCPU_START_INT_RAW` reader - RISCV_START_INT interrupt raw bit"]
16pub type COCPU_START_INT_RAW_R = crate::BitReader;
17#[doc = "Field `COCPU_SW_INT_RAW` reader - SW_INT interrupt raw bit"]
18pub type COCPU_SW_INT_RAW_R = crate::BitReader;
19#[doc = "Field `COCPU_SWD_INT_RAW` reader - SWD_INT interrupt raw bit"]
20pub type COCPU_SWD_INT_RAW_R = crate::BitReader;
21impl R {
22    #[doc = "Bit 0 - TOUCH_DONE_INT interrupt raw bit"]
23    #[inline(always)]
24    pub fn cocpu_touch_done_int_raw(&self) -> COCPU_TOUCH_DONE_INT_RAW_R {
25        COCPU_TOUCH_DONE_INT_RAW_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - TOUCH_INACTIVE_INT interrupt raw bit"]
28    #[inline(always)]
29    pub fn cocpu_touch_inactive_int_raw(&self) -> COCPU_TOUCH_INACTIVE_INT_RAW_R {
30        COCPU_TOUCH_INACTIVE_INT_RAW_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 2 - TOUCH_ACTIVE_INT interrupt raw bit"]
33    #[inline(always)]
34    pub fn cocpu_touch_active_int_raw(&self) -> COCPU_TOUCH_ACTIVE_INT_RAW_R {
35        COCPU_TOUCH_ACTIVE_INT_RAW_R::new(((self.bits >> 2) & 1) != 0)
36    }
37    #[doc = "Bit 3 - SARADC1_DONE_INT interrupt raw bit"]
38    #[inline(always)]
39    pub fn cocpu_saradc1_int_raw(&self) -> COCPU_SARADC1_INT_RAW_R {
40        COCPU_SARADC1_INT_RAW_R::new(((self.bits >> 3) & 1) != 0)
41    }
42    #[doc = "Bit 4 - SARADC2_DONE_INT interrupt raw bit"]
43    #[inline(always)]
44    pub fn cocpu_saradc2_int_raw(&self) -> COCPU_SARADC2_INT_RAW_R {
45        COCPU_SARADC2_INT_RAW_R::new(((self.bits >> 4) & 1) != 0)
46    }
47    #[doc = "Bit 5 - TSENS_DONE_INT interrupt raw bit"]
48    #[inline(always)]
49    pub fn cocpu_tsens_int_raw(&self) -> COCPU_TSENS_INT_RAW_R {
50        COCPU_TSENS_INT_RAW_R::new(((self.bits >> 5) & 1) != 0)
51    }
52    #[doc = "Bit 6 - RISCV_START_INT interrupt raw bit"]
53    #[inline(always)]
54    pub fn cocpu_start_int_raw(&self) -> COCPU_START_INT_RAW_R {
55        COCPU_START_INT_RAW_R::new(((self.bits >> 6) & 1) != 0)
56    }
57    #[doc = "Bit 7 - SW_INT interrupt raw bit"]
58    #[inline(always)]
59    pub fn cocpu_sw_int_raw(&self) -> COCPU_SW_INT_RAW_R {
60        COCPU_SW_INT_RAW_R::new(((self.bits >> 7) & 1) != 0)
61    }
62    #[doc = "Bit 8 - SWD_INT interrupt raw bit"]
63    #[inline(always)]
64    pub fn cocpu_swd_int_raw(&self) -> COCPU_SWD_INT_RAW_R {
65        COCPU_SWD_INT_RAW_R::new(((self.bits >> 8) & 1) != 0)
66    }
67}
68#[cfg(feature = "impl-register-debug")]
69impl core::fmt::Debug for R {
70    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
71        f.debug_struct("SAR_COCPU_INT_RAW")
72            .field("cocpu_touch_done_int_raw", &self.cocpu_touch_done_int_raw())
73            .field(
74                "cocpu_touch_inactive_int_raw",
75                &self.cocpu_touch_inactive_int_raw(),
76            )
77            .field(
78                "cocpu_touch_active_int_raw",
79                &self.cocpu_touch_active_int_raw(),
80            )
81            .field("cocpu_saradc1_int_raw", &self.cocpu_saradc1_int_raw())
82            .field("cocpu_saradc2_int_raw", &self.cocpu_saradc2_int_raw())
83            .field("cocpu_tsens_int_raw", &self.cocpu_tsens_int_raw())
84            .field("cocpu_start_int_raw", &self.cocpu_start_int_raw())
85            .field("cocpu_sw_int_raw", &self.cocpu_sw_int_raw())
86            .field("cocpu_swd_int_raw", &self.cocpu_swd_int_raw())
87            .finish()
88    }
89}
90#[doc = "Interrupt raw bit of ULP-RISCV\n\nYou can [`read`](crate::Reg::read) this register and get [`sar_cocpu_int_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
91pub struct SAR_COCPU_INT_RAW_SPEC;
92impl crate::RegisterSpec for SAR_COCPU_INT_RAW_SPEC {
93    type Ux = u32;
94}
95#[doc = "`read()` method returns [`sar_cocpu_int_raw::R`](R) reader structure"]
96impl crate::Readable for SAR_COCPU_INT_RAW_SPEC {}
97#[doc = "`reset()` method sets SAR_COCPU_INT_RAW to value 0"]
98impl crate::Resettable for SAR_COCPU_INT_RAW_SPEC {
99    const RESET_VALUE: u32 = 0;
100}
esp32s2_ulp/sens/sar_cocpu_int_raw.rs

esp32s2_ulp/sens/
sar_cocpu_int_raw.rs
