1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RXFIFO_FULL` writer - Set this bit to clear the rxfifo_full_int_raw interrupt."]
4pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TXFIFO_EMPTY` writer - Set this bit to clear txfifo_empty_int_raw interrupt."]
6pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `PARITY_ERR` writer - Set this bit to clear parity_err_int_raw interrupt."]
8pub type PARITY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `FRM_ERR` writer - Set this bit to clear frm_err_int_raw interrupt."]
10pub type FRM_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `RXFIFO_OVF` writer - Set this bit to clear rxfifo_ovf_int_raw interrupt."]
12pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `DSR_CHG` writer - Set this bit to clear the dsr_chg_int_raw interrupt."]
14pub type DSR_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `CTS_CHG` writer - Set this bit to clear the cts_chg_int_raw interrupt."]
16pub type CTS_CHG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `BRK_DET` writer - Set this bit to clear the brk_det_int_raw interrupt."]
18pub type BRK_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `RXFIFO_TOUT` writer - Set this bit to clear the rxfifo_tout_int_raw interrupt."]
20pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `SW_XON` writer - Set this bit to clear the sw_xon_int_raw interrupt."]
22pub type SW_XON_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `SW_XOFF` writer - Set this bit to clear the sw_xoff_int_raw interrupt."]
24pub type SW_XOFF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `GLITCH_DET` writer - Set this bit to clear the glitch_det_int_raw interrupt."]
26pub type GLITCH_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `TX_BRK_DONE` writer - Set this bit to clear the tx_brk_done_int_raw interrupt.."]
28pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `TX_BRK_IDLE_DONE` writer - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."]
30pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `TX_DONE` writer - Set this bit to clear the tx_done_int_raw interrupt."]
32pub type TX_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `RS485_PARITY_ERR` writer - Set this bit to clear the rs485_parity_err_int_raw interrupt."]
34pub type RS485_PARITY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `RS485_FRM_ERR` writer - Set this bit to clear the rs485_frm_err_int_raw interrupt."]
36pub type RS485_FRM_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `RS485_CLASH` writer - Set this bit to clear the rs485_clash_int_raw interrupt."]
38pub type RS485_CLASH_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `AT_CMD_CHAR_DET` writer - Set this bit to clear the at_cmd_char_det_int_raw interrupt."]
40pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `WAKEUP` writer - Set this bit to clear the uart_wakeup_int_raw interrupt."]
42pub type WAKEUP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
45 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
46 write!(f, "(not readable)")
47 }
48}
49impl W {
50 #[doc = "Bit 0 - Set this bit to clear the rxfifo_full_int_raw interrupt."]
51 #[inline(always)]
52 #[must_use]
53 pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_CLR_SPEC> {
54 RXFIFO_FULL_W::new(self, 0)
55 }
56 #[doc = "Bit 1 - Set this bit to clear txfifo_empty_int_raw interrupt."]
57 #[inline(always)]
58 #[must_use]
59 pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_CLR_SPEC> {
60 TXFIFO_EMPTY_W::new(self, 1)
61 }
62 #[doc = "Bit 2 - Set this bit to clear parity_err_int_raw interrupt."]
63 #[inline(always)]
64 #[must_use]
65 pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_CLR_SPEC> {
66 PARITY_ERR_W::new(self, 2)
67 }
68 #[doc = "Bit 3 - Set this bit to clear frm_err_int_raw interrupt."]
69 #[inline(always)]
70 #[must_use]
71 pub fn frm_err(&mut self) -> FRM_ERR_W<INT_CLR_SPEC> {
72 FRM_ERR_W::new(self, 3)
73 }
74 #[doc = "Bit 4 - Set this bit to clear rxfifo_ovf_int_raw interrupt."]
75 #[inline(always)]
76 #[must_use]
77 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_CLR_SPEC> {
78 RXFIFO_OVF_W::new(self, 4)
79 }
80 #[doc = "Bit 5 - Set this bit to clear the dsr_chg_int_raw interrupt."]
81 #[inline(always)]
82 #[must_use]
83 pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_CLR_SPEC> {
84 DSR_CHG_W::new(self, 5)
85 }
86 #[doc = "Bit 6 - Set this bit to clear the cts_chg_int_raw interrupt."]
87 #[inline(always)]
88 #[must_use]
89 pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_CLR_SPEC> {
90 CTS_CHG_W::new(self, 6)
91 }
92 #[doc = "Bit 7 - Set this bit to clear the brk_det_int_raw interrupt."]
93 #[inline(always)]
94 #[must_use]
95 pub fn brk_det(&mut self) -> BRK_DET_W<INT_CLR_SPEC> {
96 BRK_DET_W::new(self, 7)
97 }
98 #[doc = "Bit 8 - Set this bit to clear the rxfifo_tout_int_raw interrupt."]
99 #[inline(always)]
100 #[must_use]
101 pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_CLR_SPEC> {
102 RXFIFO_TOUT_W::new(self, 8)
103 }
104 #[doc = "Bit 9 - Set this bit to clear the sw_xon_int_raw interrupt."]
105 #[inline(always)]
106 #[must_use]
107 pub fn sw_xon(&mut self) -> SW_XON_W<INT_CLR_SPEC> {
108 SW_XON_W::new(self, 9)
109 }
110 #[doc = "Bit 10 - Set this bit to clear the sw_xoff_int_raw interrupt."]
111 #[inline(always)]
112 #[must_use]
113 pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_CLR_SPEC> {
114 SW_XOFF_W::new(self, 10)
115 }
116 #[doc = "Bit 11 - Set this bit to clear the glitch_det_int_raw interrupt."]
117 #[inline(always)]
118 #[must_use]
119 pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_CLR_SPEC> {
120 GLITCH_DET_W::new(self, 11)
121 }
122 #[doc = "Bit 12 - Set this bit to clear the tx_brk_done_int_raw interrupt.."]
123 #[inline(always)]
124 #[must_use]
125 pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_CLR_SPEC> {
126 TX_BRK_DONE_W::new(self, 12)
127 }
128 #[doc = "Bit 13 - Set this bit to clear the tx_brk_idle_done_int_raw interrupt."]
129 #[inline(always)]
130 #[must_use]
131 pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_CLR_SPEC> {
132 TX_BRK_IDLE_DONE_W::new(self, 13)
133 }
134 #[doc = "Bit 14 - Set this bit to clear the tx_done_int_raw interrupt."]
135 #[inline(always)]
136 #[must_use]
137 pub fn tx_done(&mut self) -> TX_DONE_W<INT_CLR_SPEC> {
138 TX_DONE_W::new(self, 14)
139 }
140 #[doc = "Bit 15 - Set this bit to clear the rs485_parity_err_int_raw interrupt."]
141 #[inline(always)]
142 #[must_use]
143 pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_CLR_SPEC> {
144 RS485_PARITY_ERR_W::new(self, 15)
145 }
146 #[doc = "Bit 16 - Set this bit to clear the rs485_frm_err_int_raw interrupt."]
147 #[inline(always)]
148 #[must_use]
149 pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_CLR_SPEC> {
150 RS485_FRM_ERR_W::new(self, 16)
151 }
152 #[doc = "Bit 17 - Set this bit to clear the rs485_clash_int_raw interrupt."]
153 #[inline(always)]
154 #[must_use]
155 pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_CLR_SPEC> {
156 RS485_CLASH_W::new(self, 17)
157 }
158 #[doc = "Bit 18 - Set this bit to clear the at_cmd_char_det_int_raw interrupt."]
159 #[inline(always)]
160 #[must_use]
161 pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_CLR_SPEC> {
162 AT_CMD_CHAR_DET_W::new(self, 18)
163 }
164 #[doc = "Bit 19 - Set this bit to clear the uart_wakeup_int_raw interrupt."]
165 #[inline(always)]
166 #[must_use]
167 pub fn wakeup(&mut self) -> WAKEUP_W<INT_CLR_SPEC> {
168 WAKEUP_W::new(self, 19)
169 }
170}
171#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
172pub struct INT_CLR_SPEC;
173impl crate::RegisterSpec for INT_CLR_SPEC {
174 type Ux = u32;
175}
176#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
177impl crate::Writable for INT_CLR_SPEC {
178 type Safety = crate::Unsafe;
179 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
180 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x000f_ffff;
181}
182#[doc = "`reset()` method sets INT_CLR to value 0"]
183impl crate::Resettable for INT_CLR_SPEC {
184 const RESET_VALUE: u32 = 0;
185}