esp32p4/spi1/
user1.rs

1#[doc = "Register `USER1` reader"]
2pub type R = crate::R<USER1_SPEC>;
3#[doc = "Register `USER1` writer"]
4pub type W = crate::W<USER1_SPEC>;
5#[doc = "Field `USR_DUMMY_CYCLELEN` reader - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
6pub type USR_DUMMY_CYCLELEN_R = crate::FieldReader;
7#[doc = "Field `USR_DUMMY_CYCLELEN` writer - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
8pub type USR_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
9#[doc = "Field `USR_ADDR_BITLEN` reader - The length in bits of address phase. The register value shall be (bit_num-1)."]
10pub type USR_ADDR_BITLEN_R = crate::FieldReader;
11#[doc = "Field `USR_ADDR_BITLEN` writer - The length in bits of address phase. The register value shall be (bit_num-1)."]
12pub type USR_ADDR_BITLEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
13impl R {
14    #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
15    #[inline(always)]
16    pub fn usr_dummy_cyclelen(&self) -> USR_DUMMY_CYCLELEN_R {
17        USR_DUMMY_CYCLELEN_R::new((self.bits & 0x3f) as u8)
18    }
19    #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
20    #[inline(always)]
21    pub fn usr_addr_bitlen(&self) -> USR_ADDR_BITLEN_R {
22        USR_ADDR_BITLEN_R::new(((self.bits >> 26) & 0x3f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("USER1")
29            .field(
30                "usr_dummy_cyclelen",
31                &format_args!("{}", self.usr_dummy_cyclelen().bits()),
32            )
33            .field(
34                "usr_addr_bitlen",
35                &format_args!("{}", self.usr_addr_bitlen().bits()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<USER1_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bits 0:5 - The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1)."]
48    #[inline(always)]
49    #[must_use]
50    pub fn usr_dummy_cyclelen(&mut self) -> USR_DUMMY_CYCLELEN_W<USER1_SPEC> {
51        USR_DUMMY_CYCLELEN_W::new(self, 0)
52    }
53    #[doc = "Bits 26:31 - The length in bits of address phase. The register value shall be (bit_num-1)."]
54    #[inline(always)]
55    #[must_use]
56    pub fn usr_addr_bitlen(&mut self) -> USR_ADDR_BITLEN_W<USER1_SPEC> {
57        USR_ADDR_BITLEN_W::new(self, 26)
58    }
59}
60#[doc = "SPI1 user1 register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`user1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`user1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct USER1_SPEC;
62impl crate::RegisterSpec for USER1_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`user1::R`](R) reader structure"]
66impl crate::Readable for USER1_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`user1::W`](W) writer structure"]
68impl crate::Writable for USER1_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets USER1 to value 0x5c00_0007"]
74impl crate::Resettable for USER1_SPEC {
75    const RESET_VALUE: u32 = 0x5c00_0007;
76}
esp32p4/spi1/user1.rs

esp32p4/spi1/
user1.rs
