1#[doc = "Register `TASK_ST4` reader"]
2pub type R = crate::R<TASK_ST4_SPEC>;
3#[doc = "Register `TASK_ST4` writer"]
4pub type W = crate::W<TASK_ST4_SPEC>;
5#[doc = "Field `MCPWM0_TASK_CLR0_OST_ST` reader - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
6pub type MCPWM0_TASK_CLR0_OST_ST_R = crate::BitReader;
7#[doc = "Field `MCPWM0_TASK_CLR0_OST_ST` writer - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
8pub type MCPWM0_TASK_CLR0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MCPWM0_TASK_CLR1_OST_ST` reader - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
10pub type MCPWM0_TASK_CLR1_OST_ST_R = crate::BitReader;
11#[doc = "Field `MCPWM0_TASK_CLR1_OST_ST` writer - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
12pub type MCPWM0_TASK_CLR1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `MCPWM0_TASK_CLR2_OST_ST` reader - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
14pub type MCPWM0_TASK_CLR2_OST_ST_R = crate::BitReader;
15#[doc = "Field `MCPWM0_TASK_CLR2_OST_ST` writer - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
16pub type MCPWM0_TASK_CLR2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `MCPWM0_TASK_CAP0_ST` reader - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
18pub type MCPWM0_TASK_CAP0_ST_R = crate::BitReader;
19#[doc = "Field `MCPWM0_TASK_CAP0_ST` writer - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
20pub type MCPWM0_TASK_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `MCPWM0_TASK_CAP1_ST` reader - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
22pub type MCPWM0_TASK_CAP1_ST_R = crate::BitReader;
23#[doc = "Field `MCPWM0_TASK_CAP1_ST` writer - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
24pub type MCPWM0_TASK_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `MCPWM0_TASK_CAP2_ST` reader - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
26pub type MCPWM0_TASK_CAP2_ST_R = crate::BitReader;
27#[doc = "Field `MCPWM0_TASK_CAP2_ST` writer - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
28pub type MCPWM0_TASK_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `MCPWM1_TASK_CMPR0_A_UP_ST` reader - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
30pub type MCPWM1_TASK_CMPR0_A_UP_ST_R = crate::BitReader;
31#[doc = "Field `MCPWM1_TASK_CMPR0_A_UP_ST` writer - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
32pub type MCPWM1_TASK_CMPR0_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `MCPWM1_TASK_CMPR1_A_UP_ST` reader - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
34pub type MCPWM1_TASK_CMPR1_A_UP_ST_R = crate::BitReader;
35#[doc = "Field `MCPWM1_TASK_CMPR1_A_UP_ST` writer - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
36pub type MCPWM1_TASK_CMPR1_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `MCPWM1_TASK_CMPR2_A_UP_ST` reader - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
38pub type MCPWM1_TASK_CMPR2_A_UP_ST_R = crate::BitReader;
39#[doc = "Field `MCPWM1_TASK_CMPR2_A_UP_ST` writer - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
40pub type MCPWM1_TASK_CMPR2_A_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `MCPWM1_TASK_CMPR0_B_UP_ST` reader - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
42pub type MCPWM1_TASK_CMPR0_B_UP_ST_R = crate::BitReader;
43#[doc = "Field `MCPWM1_TASK_CMPR0_B_UP_ST` writer - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
44pub type MCPWM1_TASK_CMPR0_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `MCPWM1_TASK_CMPR1_B_UP_ST` reader - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
46pub type MCPWM1_TASK_CMPR1_B_UP_ST_R = crate::BitReader;
47#[doc = "Field `MCPWM1_TASK_CMPR1_B_UP_ST` writer - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
48pub type MCPWM1_TASK_CMPR1_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MCPWM1_TASK_CMPR2_B_UP_ST` reader - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
50pub type MCPWM1_TASK_CMPR2_B_UP_ST_R = crate::BitReader;
51#[doc = "Field `MCPWM1_TASK_CMPR2_B_UP_ST` writer - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
52pub type MCPWM1_TASK_CMPR2_B_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `MCPWM1_TASK_GEN_STOP_ST` reader - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
54pub type MCPWM1_TASK_GEN_STOP_ST_R = crate::BitReader;
55#[doc = "Field `MCPWM1_TASK_GEN_STOP_ST` writer - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
56pub type MCPWM1_TASK_GEN_STOP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `MCPWM1_TASK_TIMER0_SYN_ST` reader - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
58pub type MCPWM1_TASK_TIMER0_SYN_ST_R = crate::BitReader;
59#[doc = "Field `MCPWM1_TASK_TIMER0_SYN_ST` writer - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
60pub type MCPWM1_TASK_TIMER0_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `MCPWM1_TASK_TIMER1_SYN_ST` reader - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
62pub type MCPWM1_TASK_TIMER1_SYN_ST_R = crate::BitReader;
63#[doc = "Field `MCPWM1_TASK_TIMER1_SYN_ST` writer - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
64pub type MCPWM1_TASK_TIMER1_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `MCPWM1_TASK_TIMER2_SYN_ST` reader - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
66pub type MCPWM1_TASK_TIMER2_SYN_ST_R = crate::BitReader;
67#[doc = "Field `MCPWM1_TASK_TIMER2_SYN_ST` writer - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
68pub type MCPWM1_TASK_TIMER2_SYN_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `MCPWM1_TASK_TIMER0_PERIOD_UP_ST` reader - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
70pub type MCPWM1_TASK_TIMER0_PERIOD_UP_ST_R = crate::BitReader;
71#[doc = "Field `MCPWM1_TASK_TIMER0_PERIOD_UP_ST` writer - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
72pub type MCPWM1_TASK_TIMER0_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `MCPWM1_TASK_TIMER1_PERIOD_UP_ST` reader - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
74pub type MCPWM1_TASK_TIMER1_PERIOD_UP_ST_R = crate::BitReader;
75#[doc = "Field `MCPWM1_TASK_TIMER1_PERIOD_UP_ST` writer - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
76pub type MCPWM1_TASK_TIMER1_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `MCPWM1_TASK_TIMER2_PERIOD_UP_ST` reader - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
78pub type MCPWM1_TASK_TIMER2_PERIOD_UP_ST_R = crate::BitReader;
79#[doc = "Field `MCPWM1_TASK_TIMER2_PERIOD_UP_ST` writer - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
80pub type MCPWM1_TASK_TIMER2_PERIOD_UP_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `MCPWM1_TASK_TZ0_OST_ST` reader - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
82pub type MCPWM1_TASK_TZ0_OST_ST_R = crate::BitReader;
83#[doc = "Field `MCPWM1_TASK_TZ0_OST_ST` writer - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
84pub type MCPWM1_TASK_TZ0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `MCPWM1_TASK_TZ1_OST_ST` reader - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
86pub type MCPWM1_TASK_TZ1_OST_ST_R = crate::BitReader;
87#[doc = "Field `MCPWM1_TASK_TZ1_OST_ST` writer - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
88pub type MCPWM1_TASK_TZ1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `MCPWM1_TASK_TZ2_OST_ST` reader - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
90pub type MCPWM1_TASK_TZ2_OST_ST_R = crate::BitReader;
91#[doc = "Field `MCPWM1_TASK_TZ2_OST_ST` writer - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
92pub type MCPWM1_TASK_TZ2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
93#[doc = "Field `MCPWM1_TASK_CLR0_OST_ST` reader - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
94pub type MCPWM1_TASK_CLR0_OST_ST_R = crate::BitReader;
95#[doc = "Field `MCPWM1_TASK_CLR0_OST_ST` writer - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
96pub type MCPWM1_TASK_CLR0_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
97#[doc = "Field `MCPWM1_TASK_CLR1_OST_ST` reader - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
98pub type MCPWM1_TASK_CLR1_OST_ST_R = crate::BitReader;
99#[doc = "Field `MCPWM1_TASK_CLR1_OST_ST` writer - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
100pub type MCPWM1_TASK_CLR1_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
101#[doc = "Field `MCPWM1_TASK_CLR2_OST_ST` reader - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
102pub type MCPWM1_TASK_CLR2_OST_ST_R = crate::BitReader;
103#[doc = "Field `MCPWM1_TASK_CLR2_OST_ST` writer - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
104pub type MCPWM1_TASK_CLR2_OST_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
105#[doc = "Field `MCPWM1_TASK_CAP0_ST` reader - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
106pub type MCPWM1_TASK_CAP0_ST_R = crate::BitReader;
107#[doc = "Field `MCPWM1_TASK_CAP0_ST` writer - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
108pub type MCPWM1_TASK_CAP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
109#[doc = "Field `MCPWM1_TASK_CAP1_ST` reader - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
110pub type MCPWM1_TASK_CAP1_ST_R = crate::BitReader;
111#[doc = "Field `MCPWM1_TASK_CAP1_ST` writer - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
112pub type MCPWM1_TASK_CAP1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
113#[doc = "Field `MCPWM1_TASK_CAP2_ST` reader - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
114pub type MCPWM1_TASK_CAP2_ST_R = crate::BitReader;
115#[doc = "Field `MCPWM1_TASK_CAP2_ST` writer - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
116pub type MCPWM1_TASK_CAP2_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
117#[doc = "Field `ADC_TASK_SAMPLE0_ST` reader - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
118pub type ADC_TASK_SAMPLE0_ST_R = crate::BitReader;
119#[doc = "Field `ADC_TASK_SAMPLE0_ST` writer - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
120pub type ADC_TASK_SAMPLE0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
121#[doc = "Field `ADC_TASK_SAMPLE1_ST` reader - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
122pub type ADC_TASK_SAMPLE1_ST_R = crate::BitReader;
123#[doc = "Field `ADC_TASK_SAMPLE1_ST` writer - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
124pub type ADC_TASK_SAMPLE1_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
125#[doc = "Field `ADC_TASK_START0_ST` reader - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
126pub type ADC_TASK_START0_ST_R = crate::BitReader;
127#[doc = "Field `ADC_TASK_START0_ST` writer - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
128pub type ADC_TASK_START0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
129#[doc = "Field `ADC_TASK_STOP0_ST` reader - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
130pub type ADC_TASK_STOP0_ST_R = crate::BitReader;
131#[doc = "Field `ADC_TASK_STOP0_ST` writer - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
132pub type ADC_TASK_STOP0_ST_W<'a, REG> = crate::BitWriter<'a, REG>;
133impl R {
134 #[doc = "Bit 0 - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
135 #[inline(always)]
136 pub fn mcpwm0_task_clr0_ost_st(&self) -> MCPWM0_TASK_CLR0_OST_ST_R {
137 MCPWM0_TASK_CLR0_OST_ST_R::new((self.bits & 1) != 0)
138 }
139 #[doc = "Bit 1 - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
140 #[inline(always)]
141 pub fn mcpwm0_task_clr1_ost_st(&self) -> MCPWM0_TASK_CLR1_OST_ST_R {
142 MCPWM0_TASK_CLR1_OST_ST_R::new(((self.bits >> 1) & 1) != 0)
143 }
144 #[doc = "Bit 2 - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
145 #[inline(always)]
146 pub fn mcpwm0_task_clr2_ost_st(&self) -> MCPWM0_TASK_CLR2_OST_ST_R {
147 MCPWM0_TASK_CLR2_OST_ST_R::new(((self.bits >> 2) & 1) != 0)
148 }
149 #[doc = "Bit 3 - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
150 #[inline(always)]
151 pub fn mcpwm0_task_cap0_st(&self) -> MCPWM0_TASK_CAP0_ST_R {
152 MCPWM0_TASK_CAP0_ST_R::new(((self.bits >> 3) & 1) != 0)
153 }
154 #[doc = "Bit 4 - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
155 #[inline(always)]
156 pub fn mcpwm0_task_cap1_st(&self) -> MCPWM0_TASK_CAP1_ST_R {
157 MCPWM0_TASK_CAP1_ST_R::new(((self.bits >> 4) & 1) != 0)
158 }
159 #[doc = "Bit 5 - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
160 #[inline(always)]
161 pub fn mcpwm0_task_cap2_st(&self) -> MCPWM0_TASK_CAP2_ST_R {
162 MCPWM0_TASK_CAP2_ST_R::new(((self.bits >> 5) & 1) != 0)
163 }
164 #[doc = "Bit 6 - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
165 #[inline(always)]
166 pub fn mcpwm1_task_cmpr0_a_up_st(&self) -> MCPWM1_TASK_CMPR0_A_UP_ST_R {
167 MCPWM1_TASK_CMPR0_A_UP_ST_R::new(((self.bits >> 6) & 1) != 0)
168 }
169 #[doc = "Bit 7 - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
170 #[inline(always)]
171 pub fn mcpwm1_task_cmpr1_a_up_st(&self) -> MCPWM1_TASK_CMPR1_A_UP_ST_R {
172 MCPWM1_TASK_CMPR1_A_UP_ST_R::new(((self.bits >> 7) & 1) != 0)
173 }
174 #[doc = "Bit 8 - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
175 #[inline(always)]
176 pub fn mcpwm1_task_cmpr2_a_up_st(&self) -> MCPWM1_TASK_CMPR2_A_UP_ST_R {
177 MCPWM1_TASK_CMPR2_A_UP_ST_R::new(((self.bits >> 8) & 1) != 0)
178 }
179 #[doc = "Bit 9 - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
180 #[inline(always)]
181 pub fn mcpwm1_task_cmpr0_b_up_st(&self) -> MCPWM1_TASK_CMPR0_B_UP_ST_R {
182 MCPWM1_TASK_CMPR0_B_UP_ST_R::new(((self.bits >> 9) & 1) != 0)
183 }
184 #[doc = "Bit 10 - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
185 #[inline(always)]
186 pub fn mcpwm1_task_cmpr1_b_up_st(&self) -> MCPWM1_TASK_CMPR1_B_UP_ST_R {
187 MCPWM1_TASK_CMPR1_B_UP_ST_R::new(((self.bits >> 10) & 1) != 0)
188 }
189 #[doc = "Bit 11 - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
190 #[inline(always)]
191 pub fn mcpwm1_task_cmpr2_b_up_st(&self) -> MCPWM1_TASK_CMPR2_B_UP_ST_R {
192 MCPWM1_TASK_CMPR2_B_UP_ST_R::new(((self.bits >> 11) & 1) != 0)
193 }
194 #[doc = "Bit 12 - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
195 #[inline(always)]
196 pub fn mcpwm1_task_gen_stop_st(&self) -> MCPWM1_TASK_GEN_STOP_ST_R {
197 MCPWM1_TASK_GEN_STOP_ST_R::new(((self.bits >> 12) & 1) != 0)
198 }
199 #[doc = "Bit 13 - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
200 #[inline(always)]
201 pub fn mcpwm1_task_timer0_syn_st(&self) -> MCPWM1_TASK_TIMER0_SYN_ST_R {
202 MCPWM1_TASK_TIMER0_SYN_ST_R::new(((self.bits >> 13) & 1) != 0)
203 }
204 #[doc = "Bit 14 - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
205 #[inline(always)]
206 pub fn mcpwm1_task_timer1_syn_st(&self) -> MCPWM1_TASK_TIMER1_SYN_ST_R {
207 MCPWM1_TASK_TIMER1_SYN_ST_R::new(((self.bits >> 14) & 1) != 0)
208 }
209 #[doc = "Bit 15 - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
210 #[inline(always)]
211 pub fn mcpwm1_task_timer2_syn_st(&self) -> MCPWM1_TASK_TIMER2_SYN_ST_R {
212 MCPWM1_TASK_TIMER2_SYN_ST_R::new(((self.bits >> 15) & 1) != 0)
213 }
214 #[doc = "Bit 16 - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
215 #[inline(always)]
216 pub fn mcpwm1_task_timer0_period_up_st(&self) -> MCPWM1_TASK_TIMER0_PERIOD_UP_ST_R {
217 MCPWM1_TASK_TIMER0_PERIOD_UP_ST_R::new(((self.bits >> 16) & 1) != 0)
218 }
219 #[doc = "Bit 17 - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
220 #[inline(always)]
221 pub fn mcpwm1_task_timer1_period_up_st(&self) -> MCPWM1_TASK_TIMER1_PERIOD_UP_ST_R {
222 MCPWM1_TASK_TIMER1_PERIOD_UP_ST_R::new(((self.bits >> 17) & 1) != 0)
223 }
224 #[doc = "Bit 18 - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
225 #[inline(always)]
226 pub fn mcpwm1_task_timer2_period_up_st(&self) -> MCPWM1_TASK_TIMER2_PERIOD_UP_ST_R {
227 MCPWM1_TASK_TIMER2_PERIOD_UP_ST_R::new(((self.bits >> 18) & 1) != 0)
228 }
229 #[doc = "Bit 19 - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
230 #[inline(always)]
231 pub fn mcpwm1_task_tz0_ost_st(&self) -> MCPWM1_TASK_TZ0_OST_ST_R {
232 MCPWM1_TASK_TZ0_OST_ST_R::new(((self.bits >> 19) & 1) != 0)
233 }
234 #[doc = "Bit 20 - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
235 #[inline(always)]
236 pub fn mcpwm1_task_tz1_ost_st(&self) -> MCPWM1_TASK_TZ1_OST_ST_R {
237 MCPWM1_TASK_TZ1_OST_ST_R::new(((self.bits >> 20) & 1) != 0)
238 }
239 #[doc = "Bit 21 - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
240 #[inline(always)]
241 pub fn mcpwm1_task_tz2_ost_st(&self) -> MCPWM1_TASK_TZ2_OST_ST_R {
242 MCPWM1_TASK_TZ2_OST_ST_R::new(((self.bits >> 21) & 1) != 0)
243 }
244 #[doc = "Bit 22 - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
245 #[inline(always)]
246 pub fn mcpwm1_task_clr0_ost_st(&self) -> MCPWM1_TASK_CLR0_OST_ST_R {
247 MCPWM1_TASK_CLR0_OST_ST_R::new(((self.bits >> 22) & 1) != 0)
248 }
249 #[doc = "Bit 23 - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
250 #[inline(always)]
251 pub fn mcpwm1_task_clr1_ost_st(&self) -> MCPWM1_TASK_CLR1_OST_ST_R {
252 MCPWM1_TASK_CLR1_OST_ST_R::new(((self.bits >> 23) & 1) != 0)
253 }
254 #[doc = "Bit 24 - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
255 #[inline(always)]
256 pub fn mcpwm1_task_clr2_ost_st(&self) -> MCPWM1_TASK_CLR2_OST_ST_R {
257 MCPWM1_TASK_CLR2_OST_ST_R::new(((self.bits >> 24) & 1) != 0)
258 }
259 #[doc = "Bit 25 - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
260 #[inline(always)]
261 pub fn mcpwm1_task_cap0_st(&self) -> MCPWM1_TASK_CAP0_ST_R {
262 MCPWM1_TASK_CAP0_ST_R::new(((self.bits >> 25) & 1) != 0)
263 }
264 #[doc = "Bit 26 - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
265 #[inline(always)]
266 pub fn mcpwm1_task_cap1_st(&self) -> MCPWM1_TASK_CAP1_ST_R {
267 MCPWM1_TASK_CAP1_ST_R::new(((self.bits >> 26) & 1) != 0)
268 }
269 #[doc = "Bit 27 - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
270 #[inline(always)]
271 pub fn mcpwm1_task_cap2_st(&self) -> MCPWM1_TASK_CAP2_ST_R {
272 MCPWM1_TASK_CAP2_ST_R::new(((self.bits >> 27) & 1) != 0)
273 }
274 #[doc = "Bit 28 - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
275 #[inline(always)]
276 pub fn adc_task_sample0_st(&self) -> ADC_TASK_SAMPLE0_ST_R {
277 ADC_TASK_SAMPLE0_ST_R::new(((self.bits >> 28) & 1) != 0)
278 }
279 #[doc = "Bit 29 - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
280 #[inline(always)]
281 pub fn adc_task_sample1_st(&self) -> ADC_TASK_SAMPLE1_ST_R {
282 ADC_TASK_SAMPLE1_ST_R::new(((self.bits >> 29) & 1) != 0)
283 }
284 #[doc = "Bit 30 - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
285 #[inline(always)]
286 pub fn adc_task_start0_st(&self) -> ADC_TASK_START0_ST_R {
287 ADC_TASK_START0_ST_R::new(((self.bits >> 30) & 1) != 0)
288 }
289 #[doc = "Bit 31 - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
290 #[inline(always)]
291 pub fn adc_task_stop0_st(&self) -> ADC_TASK_STOP0_ST_R {
292 ADC_TASK_STOP0_ST_R::new(((self.bits >> 31) & 1) != 0)
293 }
294}
295#[cfg(feature = "impl-register-debug")]
296impl core::fmt::Debug for R {
297 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
298 f.debug_struct("TASK_ST4")
299 .field(
300 "mcpwm0_task_clr0_ost_st",
301 &format_args!("{}", self.mcpwm0_task_clr0_ost_st().bit()),
302 )
303 .field(
304 "mcpwm0_task_clr1_ost_st",
305 &format_args!("{}", self.mcpwm0_task_clr1_ost_st().bit()),
306 )
307 .field(
308 "mcpwm0_task_clr2_ost_st",
309 &format_args!("{}", self.mcpwm0_task_clr2_ost_st().bit()),
310 )
311 .field(
312 "mcpwm0_task_cap0_st",
313 &format_args!("{}", self.mcpwm0_task_cap0_st().bit()),
314 )
315 .field(
316 "mcpwm0_task_cap1_st",
317 &format_args!("{}", self.mcpwm0_task_cap1_st().bit()),
318 )
319 .field(
320 "mcpwm0_task_cap2_st",
321 &format_args!("{}", self.mcpwm0_task_cap2_st().bit()),
322 )
323 .field(
324 "mcpwm1_task_cmpr0_a_up_st",
325 &format_args!("{}", self.mcpwm1_task_cmpr0_a_up_st().bit()),
326 )
327 .field(
328 "mcpwm1_task_cmpr1_a_up_st",
329 &format_args!("{}", self.mcpwm1_task_cmpr1_a_up_st().bit()),
330 )
331 .field(
332 "mcpwm1_task_cmpr2_a_up_st",
333 &format_args!("{}", self.mcpwm1_task_cmpr2_a_up_st().bit()),
334 )
335 .field(
336 "mcpwm1_task_cmpr0_b_up_st",
337 &format_args!("{}", self.mcpwm1_task_cmpr0_b_up_st().bit()),
338 )
339 .field(
340 "mcpwm1_task_cmpr1_b_up_st",
341 &format_args!("{}", self.mcpwm1_task_cmpr1_b_up_st().bit()),
342 )
343 .field(
344 "mcpwm1_task_cmpr2_b_up_st",
345 &format_args!("{}", self.mcpwm1_task_cmpr2_b_up_st().bit()),
346 )
347 .field(
348 "mcpwm1_task_gen_stop_st",
349 &format_args!("{}", self.mcpwm1_task_gen_stop_st().bit()),
350 )
351 .field(
352 "mcpwm1_task_timer0_syn_st",
353 &format_args!("{}", self.mcpwm1_task_timer0_syn_st().bit()),
354 )
355 .field(
356 "mcpwm1_task_timer1_syn_st",
357 &format_args!("{}", self.mcpwm1_task_timer1_syn_st().bit()),
358 )
359 .field(
360 "mcpwm1_task_timer2_syn_st",
361 &format_args!("{}", self.mcpwm1_task_timer2_syn_st().bit()),
362 )
363 .field(
364 "mcpwm1_task_timer0_period_up_st",
365 &format_args!("{}", self.mcpwm1_task_timer0_period_up_st().bit()),
366 )
367 .field(
368 "mcpwm1_task_timer1_period_up_st",
369 &format_args!("{}", self.mcpwm1_task_timer1_period_up_st().bit()),
370 )
371 .field(
372 "mcpwm1_task_timer2_period_up_st",
373 &format_args!("{}", self.mcpwm1_task_timer2_period_up_st().bit()),
374 )
375 .field(
376 "mcpwm1_task_tz0_ost_st",
377 &format_args!("{}", self.mcpwm1_task_tz0_ost_st().bit()),
378 )
379 .field(
380 "mcpwm1_task_tz1_ost_st",
381 &format_args!("{}", self.mcpwm1_task_tz1_ost_st().bit()),
382 )
383 .field(
384 "mcpwm1_task_tz2_ost_st",
385 &format_args!("{}", self.mcpwm1_task_tz2_ost_st().bit()),
386 )
387 .field(
388 "mcpwm1_task_clr0_ost_st",
389 &format_args!("{}", self.mcpwm1_task_clr0_ost_st().bit()),
390 )
391 .field(
392 "mcpwm1_task_clr1_ost_st",
393 &format_args!("{}", self.mcpwm1_task_clr1_ost_st().bit()),
394 )
395 .field(
396 "mcpwm1_task_clr2_ost_st",
397 &format_args!("{}", self.mcpwm1_task_clr2_ost_st().bit()),
398 )
399 .field(
400 "mcpwm1_task_cap0_st",
401 &format_args!("{}", self.mcpwm1_task_cap0_st().bit()),
402 )
403 .field(
404 "mcpwm1_task_cap1_st",
405 &format_args!("{}", self.mcpwm1_task_cap1_st().bit()),
406 )
407 .field(
408 "mcpwm1_task_cap2_st",
409 &format_args!("{}", self.mcpwm1_task_cap2_st().bit()),
410 )
411 .field(
412 "adc_task_sample0_st",
413 &format_args!("{}", self.adc_task_sample0_st().bit()),
414 )
415 .field(
416 "adc_task_sample1_st",
417 &format_args!("{}", self.adc_task_sample1_st().bit()),
418 )
419 .field(
420 "adc_task_start0_st",
421 &format_args!("{}", self.adc_task_start0_st().bit()),
422 )
423 .field(
424 "adc_task_stop0_st",
425 &format_args!("{}", self.adc_task_stop0_st().bit()),
426 )
427 .finish()
428 }
429}
430#[cfg(feature = "impl-register-debug")]
431impl core::fmt::Debug for crate::generic::Reg<TASK_ST4_SPEC> {
432 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
433 core::fmt::Debug::fmt(&self.read(), f)
434 }
435}
436impl W {
437 #[doc = "Bit 0 - Represents MCPWM0_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
438 #[inline(always)]
439 #[must_use]
440 pub fn mcpwm0_task_clr0_ost_st(&mut self) -> MCPWM0_TASK_CLR0_OST_ST_W<TASK_ST4_SPEC> {
441 MCPWM0_TASK_CLR0_OST_ST_W::new(self, 0)
442 }
443 #[doc = "Bit 1 - Represents MCPWM0_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
444 #[inline(always)]
445 #[must_use]
446 pub fn mcpwm0_task_clr1_ost_st(&mut self) -> MCPWM0_TASK_CLR1_OST_ST_W<TASK_ST4_SPEC> {
447 MCPWM0_TASK_CLR1_OST_ST_W::new(self, 1)
448 }
449 #[doc = "Bit 2 - Represents MCPWM0_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
450 #[inline(always)]
451 #[must_use]
452 pub fn mcpwm0_task_clr2_ost_st(&mut self) -> MCPWM0_TASK_CLR2_OST_ST_W<TASK_ST4_SPEC> {
453 MCPWM0_TASK_CLR2_OST_ST_W::new(self, 2)
454 }
455 #[doc = "Bit 3 - Represents MCPWM0_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
456 #[inline(always)]
457 #[must_use]
458 pub fn mcpwm0_task_cap0_st(&mut self) -> MCPWM0_TASK_CAP0_ST_W<TASK_ST4_SPEC> {
459 MCPWM0_TASK_CAP0_ST_W::new(self, 3)
460 }
461 #[doc = "Bit 4 - Represents MCPWM0_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
462 #[inline(always)]
463 #[must_use]
464 pub fn mcpwm0_task_cap1_st(&mut self) -> MCPWM0_TASK_CAP1_ST_W<TASK_ST4_SPEC> {
465 MCPWM0_TASK_CAP1_ST_W::new(self, 4)
466 }
467 #[doc = "Bit 5 - Represents MCPWM0_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
468 #[inline(always)]
469 #[must_use]
470 pub fn mcpwm0_task_cap2_st(&mut self) -> MCPWM0_TASK_CAP2_ST_W<TASK_ST4_SPEC> {
471 MCPWM0_TASK_CAP2_ST_W::new(self, 5)
472 }
473 #[doc = "Bit 6 - Represents MCPWM1_task_cmpr0_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
474 #[inline(always)]
475 #[must_use]
476 pub fn mcpwm1_task_cmpr0_a_up_st(&mut self) -> MCPWM1_TASK_CMPR0_A_UP_ST_W<TASK_ST4_SPEC> {
477 MCPWM1_TASK_CMPR0_A_UP_ST_W::new(self, 6)
478 }
479 #[doc = "Bit 7 - Represents MCPWM1_task_cmpr1_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
480 #[inline(always)]
481 #[must_use]
482 pub fn mcpwm1_task_cmpr1_a_up_st(&mut self) -> MCPWM1_TASK_CMPR1_A_UP_ST_W<TASK_ST4_SPEC> {
483 MCPWM1_TASK_CMPR1_A_UP_ST_W::new(self, 7)
484 }
485 #[doc = "Bit 8 - Represents MCPWM1_task_cmpr2_a_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
486 #[inline(always)]
487 #[must_use]
488 pub fn mcpwm1_task_cmpr2_a_up_st(&mut self) -> MCPWM1_TASK_CMPR2_A_UP_ST_W<TASK_ST4_SPEC> {
489 MCPWM1_TASK_CMPR2_A_UP_ST_W::new(self, 8)
490 }
491 #[doc = "Bit 9 - Represents MCPWM1_task_cmpr0_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
492 #[inline(always)]
493 #[must_use]
494 pub fn mcpwm1_task_cmpr0_b_up_st(&mut self) -> MCPWM1_TASK_CMPR0_B_UP_ST_W<TASK_ST4_SPEC> {
495 MCPWM1_TASK_CMPR0_B_UP_ST_W::new(self, 9)
496 }
497 #[doc = "Bit 10 - Represents MCPWM1_task_cmpr1_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
498 #[inline(always)]
499 #[must_use]
500 pub fn mcpwm1_task_cmpr1_b_up_st(&mut self) -> MCPWM1_TASK_CMPR1_B_UP_ST_W<TASK_ST4_SPEC> {
501 MCPWM1_TASK_CMPR1_B_UP_ST_W::new(self, 10)
502 }
503 #[doc = "Bit 11 - Represents MCPWM1_task_cmpr2_b_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
504 #[inline(always)]
505 #[must_use]
506 pub fn mcpwm1_task_cmpr2_b_up_st(&mut self) -> MCPWM1_TASK_CMPR2_B_UP_ST_W<TASK_ST4_SPEC> {
507 MCPWM1_TASK_CMPR2_B_UP_ST_W::new(self, 11)
508 }
509 #[doc = "Bit 12 - Represents MCPWM1_task_gen_stop trigger status.\\\\0: Not triggered\\\\1: Triggered"]
510 #[inline(always)]
511 #[must_use]
512 pub fn mcpwm1_task_gen_stop_st(&mut self) -> MCPWM1_TASK_GEN_STOP_ST_W<TASK_ST4_SPEC> {
513 MCPWM1_TASK_GEN_STOP_ST_W::new(self, 12)
514 }
515 #[doc = "Bit 13 - Represents MCPWM1_task_timer0_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
516 #[inline(always)]
517 #[must_use]
518 pub fn mcpwm1_task_timer0_syn_st(&mut self) -> MCPWM1_TASK_TIMER0_SYN_ST_W<TASK_ST4_SPEC> {
519 MCPWM1_TASK_TIMER0_SYN_ST_W::new(self, 13)
520 }
521 #[doc = "Bit 14 - Represents MCPWM1_task_timer1_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
522 #[inline(always)]
523 #[must_use]
524 pub fn mcpwm1_task_timer1_syn_st(&mut self) -> MCPWM1_TASK_TIMER1_SYN_ST_W<TASK_ST4_SPEC> {
525 MCPWM1_TASK_TIMER1_SYN_ST_W::new(self, 14)
526 }
527 #[doc = "Bit 15 - Represents MCPWM1_task_timer2_syn trigger status.\\\\0: Not triggered\\\\1: Triggered"]
528 #[inline(always)]
529 #[must_use]
530 pub fn mcpwm1_task_timer2_syn_st(&mut self) -> MCPWM1_TASK_TIMER2_SYN_ST_W<TASK_ST4_SPEC> {
531 MCPWM1_TASK_TIMER2_SYN_ST_W::new(self, 15)
532 }
533 #[doc = "Bit 16 - Represents MCPWM1_task_timer0_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
534 #[inline(always)]
535 #[must_use]
536 pub fn mcpwm1_task_timer0_period_up_st(
537 &mut self,
538 ) -> MCPWM1_TASK_TIMER0_PERIOD_UP_ST_W<TASK_ST4_SPEC> {
539 MCPWM1_TASK_TIMER0_PERIOD_UP_ST_W::new(self, 16)
540 }
541 #[doc = "Bit 17 - Represents MCPWM1_task_timer1_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
542 #[inline(always)]
543 #[must_use]
544 pub fn mcpwm1_task_timer1_period_up_st(
545 &mut self,
546 ) -> MCPWM1_TASK_TIMER1_PERIOD_UP_ST_W<TASK_ST4_SPEC> {
547 MCPWM1_TASK_TIMER1_PERIOD_UP_ST_W::new(self, 17)
548 }
549 #[doc = "Bit 18 - Represents MCPWM1_task_timer2_period_up trigger status.\\\\0: Not triggered\\\\1: Triggered"]
550 #[inline(always)]
551 #[must_use]
552 pub fn mcpwm1_task_timer2_period_up_st(
553 &mut self,
554 ) -> MCPWM1_TASK_TIMER2_PERIOD_UP_ST_W<TASK_ST4_SPEC> {
555 MCPWM1_TASK_TIMER2_PERIOD_UP_ST_W::new(self, 18)
556 }
557 #[doc = "Bit 19 - Represents MCPWM1_task_tz0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
558 #[inline(always)]
559 #[must_use]
560 pub fn mcpwm1_task_tz0_ost_st(&mut self) -> MCPWM1_TASK_TZ0_OST_ST_W<TASK_ST4_SPEC> {
561 MCPWM1_TASK_TZ0_OST_ST_W::new(self, 19)
562 }
563 #[doc = "Bit 20 - Represents MCPWM1_task_tz1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
564 #[inline(always)]
565 #[must_use]
566 pub fn mcpwm1_task_tz1_ost_st(&mut self) -> MCPWM1_TASK_TZ1_OST_ST_W<TASK_ST4_SPEC> {
567 MCPWM1_TASK_TZ1_OST_ST_W::new(self, 20)
568 }
569 #[doc = "Bit 21 - Represents MCPWM1_task_tz2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
570 #[inline(always)]
571 #[must_use]
572 pub fn mcpwm1_task_tz2_ost_st(&mut self) -> MCPWM1_TASK_TZ2_OST_ST_W<TASK_ST4_SPEC> {
573 MCPWM1_TASK_TZ2_OST_ST_W::new(self, 21)
574 }
575 #[doc = "Bit 22 - Represents MCPWM1_task_clr0_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
576 #[inline(always)]
577 #[must_use]
578 pub fn mcpwm1_task_clr0_ost_st(&mut self) -> MCPWM1_TASK_CLR0_OST_ST_W<TASK_ST4_SPEC> {
579 MCPWM1_TASK_CLR0_OST_ST_W::new(self, 22)
580 }
581 #[doc = "Bit 23 - Represents MCPWM1_task_clr1_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
582 #[inline(always)]
583 #[must_use]
584 pub fn mcpwm1_task_clr1_ost_st(&mut self) -> MCPWM1_TASK_CLR1_OST_ST_W<TASK_ST4_SPEC> {
585 MCPWM1_TASK_CLR1_OST_ST_W::new(self, 23)
586 }
587 #[doc = "Bit 24 - Represents MCPWM1_task_clr2_ost trigger status.\\\\0: Not triggered\\\\1: Triggered"]
588 #[inline(always)]
589 #[must_use]
590 pub fn mcpwm1_task_clr2_ost_st(&mut self) -> MCPWM1_TASK_CLR2_OST_ST_W<TASK_ST4_SPEC> {
591 MCPWM1_TASK_CLR2_OST_ST_W::new(self, 24)
592 }
593 #[doc = "Bit 25 - Represents MCPWM1_task_cap0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
594 #[inline(always)]
595 #[must_use]
596 pub fn mcpwm1_task_cap0_st(&mut self) -> MCPWM1_TASK_CAP0_ST_W<TASK_ST4_SPEC> {
597 MCPWM1_TASK_CAP0_ST_W::new(self, 25)
598 }
599 #[doc = "Bit 26 - Represents MCPWM1_task_cap1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
600 #[inline(always)]
601 #[must_use]
602 pub fn mcpwm1_task_cap1_st(&mut self) -> MCPWM1_TASK_CAP1_ST_W<TASK_ST4_SPEC> {
603 MCPWM1_TASK_CAP1_ST_W::new(self, 26)
604 }
605 #[doc = "Bit 27 - Represents MCPWM1_task_cap2 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
606 #[inline(always)]
607 #[must_use]
608 pub fn mcpwm1_task_cap2_st(&mut self) -> MCPWM1_TASK_CAP2_ST_W<TASK_ST4_SPEC> {
609 MCPWM1_TASK_CAP2_ST_W::new(self, 27)
610 }
611 #[doc = "Bit 28 - Represents ADC_task_sample0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
612 #[inline(always)]
613 #[must_use]
614 pub fn adc_task_sample0_st(&mut self) -> ADC_TASK_SAMPLE0_ST_W<TASK_ST4_SPEC> {
615 ADC_TASK_SAMPLE0_ST_W::new(self, 28)
616 }
617 #[doc = "Bit 29 - Represents ADC_task_sample1 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
618 #[inline(always)]
619 #[must_use]
620 pub fn adc_task_sample1_st(&mut self) -> ADC_TASK_SAMPLE1_ST_W<TASK_ST4_SPEC> {
621 ADC_TASK_SAMPLE1_ST_W::new(self, 29)
622 }
623 #[doc = "Bit 30 - Represents ADC_task_start0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
624 #[inline(always)]
625 #[must_use]
626 pub fn adc_task_start0_st(&mut self) -> ADC_TASK_START0_ST_W<TASK_ST4_SPEC> {
627 ADC_TASK_START0_ST_W::new(self, 30)
628 }
629 #[doc = "Bit 31 - Represents ADC_task_stop0 trigger status.\\\\0: Not triggered\\\\1: Triggered"]
630 #[inline(always)]
631 #[must_use]
632 pub fn adc_task_stop0_st(&mut self) -> ADC_TASK_STOP0_ST_W<TASK_ST4_SPEC> {
633 ADC_TASK_STOP0_ST_W::new(self, 31)
634 }
635}
636#[doc = "Tasks trigger status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`task_st4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`task_st4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
637pub struct TASK_ST4_SPEC;
638impl crate::RegisterSpec for TASK_ST4_SPEC {
639 type Ux = u32;
640}
641#[doc = "`read()` method returns [`task_st4::R`](R) reader structure"]
642impl crate::Readable for TASK_ST4_SPEC {}
643#[doc = "`write(|w| ..)` method takes [`task_st4::W`](W) writer structure"]
644impl crate::Writable for TASK_ST4_SPEC {
645 type Safety = crate::Unsafe;
646 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
647 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
648}
649#[doc = "`reset()` method sets TASK_ST4 to value 0"]
650impl crate::Resettable for TASK_ST4_SPEC {
651 const RESET_VALUE: u32 = 0;
652}