1#[doc = "Register `IDSTS` reader"]
2pub type R = crate::R<IDSTS_SPEC>;
3#[doc = "Register `IDSTS` writer"]
4pub type W = crate::W<IDSTS_SPEC>;
5#[doc = "Field `TI` reader - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
6pub type TI_R = crate::BitReader;
7#[doc = "Field `TI` writer - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
8pub type TI_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RI` reader - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
10pub type RI_R = crate::BitReader;
11#[doc = "Field `RI` writer - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
12pub type RI_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FBE` reader - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
14pub type FBE_R = crate::BitReader;
15#[doc = "Field `FBE` writer - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
16pub type FBE_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `DU` reader - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
18pub type DU_R = crate::BitReader;
19#[doc = "Field `DU` writer - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
20pub type DU_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CES` reader - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
22pub type CES_R = crate::BitReader;
23#[doc = "Field `CES` writer - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
24pub type CES_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `NIS` reader - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
26pub type NIS_R = crate::BitReader;
27#[doc = "Field `NIS` writer - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
28pub type NIS_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `AIS` reader - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
30pub type AIS_R = crate::BitReader;
31#[doc = "Field `AIS` writer - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
32pub type AIS_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FBE_CODE` reader - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
34pub type FBE_CODE_R = crate::FieldReader;
35#[doc = "Field `FBE_CODE` writer - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
36pub type FBE_CODE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
37#[doc = "Field `FSM` reader - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
38pub type FSM_R = crate::FieldReader;
39#[doc = "Field `FSM` writer - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
40pub type FSM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
41impl R {
42 #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
43 #[inline(always)]
44 pub fn ti(&self) -> TI_R {
45 TI_R::new((self.bits & 1) != 0)
46 }
47 #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
48 #[inline(always)]
49 pub fn ri(&self) -> RI_R {
50 RI_R::new(((self.bits >> 1) & 1) != 0)
51 }
52 #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
53 #[inline(always)]
54 pub fn fbe(&self) -> FBE_R {
55 FBE_R::new(((self.bits >> 2) & 1) != 0)
56 }
57 #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
58 #[inline(always)]
59 pub fn du(&self) -> DU_R {
60 DU_R::new(((self.bits >> 4) & 1) != 0)
61 }
62 #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
63 #[inline(always)]
64 pub fn ces(&self) -> CES_R {
65 CES_R::new(((self.bits >> 5) & 1) != 0)
66 }
67 #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
68 #[inline(always)]
69 pub fn nis(&self) -> NIS_R {
70 NIS_R::new(((self.bits >> 8) & 1) != 0)
71 }
72 #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
73 #[inline(always)]
74 pub fn ais(&self) -> AIS_R {
75 AIS_R::new(((self.bits >> 9) & 1) != 0)
76 }
77 #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
78 #[inline(always)]
79 pub fn fbe_code(&self) -> FBE_CODE_R {
80 FBE_CODE_R::new(((self.bits >> 10) & 7) as u8)
81 }
82 #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
83 #[inline(always)]
84 pub fn fsm(&self) -> FSM_R {
85 FSM_R::new(((self.bits >> 13) & 0x0f) as u8)
86 }
87}
88#[cfg(feature = "impl-register-debug")]
89impl core::fmt::Debug for R {
90 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
91 f.debug_struct("IDSTS")
92 .field("ti", &format_args!("{}", self.ti().bit()))
93 .field("ri", &format_args!("{}", self.ri().bit()))
94 .field("fbe", &format_args!("{}", self.fbe().bit()))
95 .field("du", &format_args!("{}", self.du().bit()))
96 .field("ces", &format_args!("{}", self.ces().bit()))
97 .field("nis", &format_args!("{}", self.nis().bit()))
98 .field("ais", &format_args!("{}", self.ais().bit()))
99 .field("fbe_code", &format_args!("{}", self.fbe_code().bits()))
100 .field("fsm", &format_args!("{}", self.fsm().bits()))
101 .finish()
102 }
103}
104#[cfg(feature = "impl-register-debug")]
105impl core::fmt::Debug for crate::generic::Reg<IDSTS_SPEC> {
106 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
107 core::fmt::Debug::fmt(&self.read(), f)
108 }
109}
110impl W {
111 #[doc = "Bit 0 - Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1 clears this bit."]
112 #[inline(always)]
113 #[must_use]
114 pub fn ti(&mut self) -> TI_W<IDSTS_SPEC> {
115 TI_W::new(self, 0)
116 }
117 #[doc = "Bit 1 - Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1 clears this bit."]
118 #[inline(always)]
119 #[must_use]
120 pub fn ri(&mut self) -> RI_W<IDSTS_SPEC> {
121 RI_W::new(self, 1)
122 }
123 #[doc = "Bit 2 - Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS\\[12:10\\]) . When this bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit."]
124 #[inline(always)]
125 #[must_use]
126 pub fn fbe(&mut self) -> FBE_W<IDSTS_SPEC> {
127 FBE_W::new(self, 2)
128 }
129 #[doc = "Bit 4 - Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWNER bit = 0 (DES0\\[31\\] = 0). Writing 1 clears this bit."]
130 #[inline(always)]
131 #[must_use]
132 pub fn du(&mut self) -> DU_W<IDSTS_SPEC> {
133 DU_W::new(self, 4)
134 }
135 #[doc = "Bit 5 - Card Error Summary. Indicates the status of the transaction to/from the card, also present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error; RTO : Response Timeout/Boot Ack Timeout; RCRC : Response CRC; SBE : Start Bit Error; DRTO : Data Read Timeout/BDS timeout; DCRC : Data CRC for Receive; RE : Response Error. Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit is enabled, then the IDMAC aborts on a response error."]
136 #[inline(always)]
137 #[must_use]
138 pub fn ces(&mut self) -> CES_W<IDSTS_SPEC> {
139 CES_W::new(self, 5)
140 }
141 #[doc = "Bit 8 - Normal Interrupt Summary. Logical OR of the following: IDSTS\\[0\\] : Transmit Interrupt, IDSTS\\[1\\] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this bit."]
142 #[inline(always)]
143 #[must_use]
144 pub fn nis(&mut self) -> NIS_W<IDSTS_SPEC> {
145 NIS_W::new(self, 8)
146 }
147 #[doc = "Bit 9 - Abnormal Interrupt Summary. Logical OR of the following: IDSTS\\[2\\] : Fatal Bus Interrupt, IDSTS\\[4\\] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this bit."]
148 #[inline(always)]
149 #[must_use]
150 pub fn ais(&mut self) -> AIS_W<IDSTS_SPEC> {
151 AIS_W::new(self, 9)
152 }
153 #[doc = "Bits 10:12 - Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid only when the Fatal Bus Error bit IDSTS\\[2\\] is set. This field does not generate an interrupt. 001: Host Abort received during transmission; 010: Host Abort received during reception; Others: Reserved."]
154 #[inline(always)]
155 #[must_use]
156 pub fn fbe_code(&mut self) -> FBE_CODE_W<IDSTS_SPEC> {
157 FBE_CODE_W::new(self, 10)
158 }
159 #[doc = "Bits 13:16 - DMAC FSM present state. 0: DMA_IDLE (idle state); 1: DMA_SUSPEND (suspend state); 2: DESC_RD (descriptor reading state); 3: DESC_CHK (descriptor checking state); 4: DMA_RD_REQ_WAIT (read-data request waiting state); 5: DMA_WR_REQ_WAIT (write-data request waiting state); 6: DMA_RD (data-read state); 7: DMA_WR (data-write state); 8: DESC_CLOSE (descriptor close state)."]
160 #[inline(always)]
161 #[must_use]
162 pub fn fsm(&mut self) -> FSM_W<IDSTS_SPEC> {
163 FSM_W::new(self, 13)
164 }
165}
166#[doc = "IDMAC status register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`idsts::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`idsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
167pub struct IDSTS_SPEC;
168impl crate::RegisterSpec for IDSTS_SPEC {
169 type Ux = u32;
170}
171#[doc = "`read()` method returns [`idsts::R`](R) reader structure"]
172impl crate::Readable for IDSTS_SPEC {}
173#[doc = "`write(|w| ..)` method takes [`idsts::W`](W) writer structure"]
174impl crate::Writable for IDSTS_SPEC {
175 type Safety = crate::Unsafe;
176 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
177 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
178}
179#[doc = "`reset()` method sets IDSTS to value 0"]
180impl crate::Resettable for IDSTS_SPEC {
181 const RESET_VALUE: u32 = 0;
182}