1#[doc = "Register `CLK_EDGE_SEL` reader"]
2pub type R = crate::R<CLK_EDGE_SEL_SPEC>;
3#[doc = "Register `CLK_EDGE_SEL` writer"]
4pub type W = crate::W<CLK_EDGE_SEL_SPEC>;
5#[doc = "Field `CCLKIN_EDGE_DRV_SEL` reader - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
6pub type CCLKIN_EDGE_DRV_SEL_R = crate::FieldReader;
7#[doc = "Field `CCLKIN_EDGE_DRV_SEL` writer - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
8pub type CCLKIN_EDGE_DRV_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
9#[doc = "Field `CCLKIN_EDGE_SAM_SEL` reader - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
10pub type CCLKIN_EDGE_SAM_SEL_R = crate::FieldReader;
11#[doc = "Field `CCLKIN_EDGE_SAM_SEL` writer - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
12pub type CCLKIN_EDGE_SAM_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `CCLKIN_EDGE_SLF_SEL` reader - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
14pub type CCLKIN_EDGE_SLF_SEL_R = crate::FieldReader;
15#[doc = "Field `CCLKIN_EDGE_SLF_SEL` writer - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
16pub type CCLKIN_EDGE_SLF_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
17#[doc = "Field `CCLLKIN_EDGE_H` reader - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
18pub type CCLLKIN_EDGE_H_R = crate::FieldReader;
19#[doc = "Field `CCLLKIN_EDGE_H` writer - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
20pub type CCLLKIN_EDGE_H_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
21#[doc = "Field `CCLLKIN_EDGE_L` reader - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
22pub type CCLLKIN_EDGE_L_R = crate::FieldReader;
23#[doc = "Field `CCLLKIN_EDGE_L` writer - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
24pub type CCLLKIN_EDGE_L_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
25#[doc = "Field `CCLLKIN_EDGE_N` reader - The clock division of cclk_in."]
26pub type CCLLKIN_EDGE_N_R = crate::FieldReader;
27#[doc = "Field `CCLLKIN_EDGE_N` writer - The clock division of cclk_in."]
28pub type CCLLKIN_EDGE_N_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
29#[doc = "Field `ESDIO_MODE` reader - Enable esdio mode."]
30pub type ESDIO_MODE_R = crate::BitReader;
31#[doc = "Field `ESDIO_MODE` writer - Enable esdio mode."]
32pub type ESDIO_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `ESD_MODE` reader - Enable esd mode."]
34pub type ESD_MODE_R = crate::BitReader;
35#[doc = "Field `ESD_MODE` writer - Enable esd mode."]
36pub type ESD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CCLK_EN` reader - Sdio clock enable."]
38pub type CCLK_EN_R = crate::BitReader;
39#[doc = "Field `CCLK_EN` writer - Sdio clock enable."]
40pub type CCLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `ULTRA_HIGH_SPEED_MODE` reader - Enable ultra high speed mode, use dll to generate clk."]
42pub type ULTRA_HIGH_SPEED_MODE_R = crate::BitReader;
43#[doc = "Field `ULTRA_HIGH_SPEED_MODE` writer - Enable ultra high speed mode, use dll to generate clk."]
44pub type ULTRA_HIGH_SPEED_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
45impl R {
46 #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
47 #[inline(always)]
48 pub fn cclkin_edge_drv_sel(&self) -> CCLKIN_EDGE_DRV_SEL_R {
49 CCLKIN_EDGE_DRV_SEL_R::new((self.bits & 7) as u8)
50 }
51 #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
52 #[inline(always)]
53 pub fn cclkin_edge_sam_sel(&self) -> CCLKIN_EDGE_SAM_SEL_R {
54 CCLKIN_EDGE_SAM_SEL_R::new(((self.bits >> 3) & 7) as u8)
55 }
56 #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
57 #[inline(always)]
58 pub fn cclkin_edge_slf_sel(&self) -> CCLKIN_EDGE_SLF_SEL_R {
59 CCLKIN_EDGE_SLF_SEL_R::new(((self.bits >> 6) & 7) as u8)
60 }
61 #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
62 #[inline(always)]
63 pub fn ccllkin_edge_h(&self) -> CCLLKIN_EDGE_H_R {
64 CCLLKIN_EDGE_H_R::new(((self.bits >> 9) & 0x0f) as u8)
65 }
66 #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
67 #[inline(always)]
68 pub fn ccllkin_edge_l(&self) -> CCLLKIN_EDGE_L_R {
69 CCLLKIN_EDGE_L_R::new(((self.bits >> 13) & 0x0f) as u8)
70 }
71 #[doc = "Bits 17:20 - The clock division of cclk_in."]
72 #[inline(always)]
73 pub fn ccllkin_edge_n(&self) -> CCLLKIN_EDGE_N_R {
74 CCLLKIN_EDGE_N_R::new(((self.bits >> 17) & 0x0f) as u8)
75 }
76 #[doc = "Bit 21 - Enable esdio mode."]
77 #[inline(always)]
78 pub fn esdio_mode(&self) -> ESDIO_MODE_R {
79 ESDIO_MODE_R::new(((self.bits >> 21) & 1) != 0)
80 }
81 #[doc = "Bit 22 - Enable esd mode."]
82 #[inline(always)]
83 pub fn esd_mode(&self) -> ESD_MODE_R {
84 ESD_MODE_R::new(((self.bits >> 22) & 1) != 0)
85 }
86 #[doc = "Bit 23 - Sdio clock enable."]
87 #[inline(always)]
88 pub fn cclk_en(&self) -> CCLK_EN_R {
89 CCLK_EN_R::new(((self.bits >> 23) & 1) != 0)
90 }
91 #[doc = "Bit 24 - Enable ultra high speed mode, use dll to generate clk."]
92 #[inline(always)]
93 pub fn ultra_high_speed_mode(&self) -> ULTRA_HIGH_SPEED_MODE_R {
94 ULTRA_HIGH_SPEED_MODE_R::new(((self.bits >> 24) & 1) != 0)
95 }
96}
97#[cfg(feature = "impl-register-debug")]
98impl core::fmt::Debug for R {
99 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
100 f.debug_struct("CLK_EDGE_SEL")
101 .field(
102 "cclkin_edge_drv_sel",
103 &format_args!("{}", self.cclkin_edge_drv_sel().bits()),
104 )
105 .field(
106 "cclkin_edge_sam_sel",
107 &format_args!("{}", self.cclkin_edge_sam_sel().bits()),
108 )
109 .field(
110 "cclkin_edge_slf_sel",
111 &format_args!("{}", self.cclkin_edge_slf_sel().bits()),
112 )
113 .field(
114 "ccllkin_edge_h",
115 &format_args!("{}", self.ccllkin_edge_h().bits()),
116 )
117 .field(
118 "ccllkin_edge_l",
119 &format_args!("{}", self.ccllkin_edge_l().bits()),
120 )
121 .field(
122 "ccllkin_edge_n",
123 &format_args!("{}", self.ccllkin_edge_n().bits()),
124 )
125 .field("esdio_mode", &format_args!("{}", self.esdio_mode().bit()))
126 .field("esd_mode", &format_args!("{}", self.esd_mode().bit()))
127 .field("cclk_en", &format_args!("{}", self.cclk_en().bit()))
128 .field(
129 "ultra_high_speed_mode",
130 &format_args!("{}", self.ultra_high_speed_mode().bit()),
131 )
132 .finish()
133 }
134}
135#[cfg(feature = "impl-register-debug")]
136impl core::fmt::Debug for crate::generic::Reg<CLK_EDGE_SEL_SPEC> {
137 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
138 core::fmt::Debug::fmt(&self.read(), f)
139 }
140}
141impl W {
142 #[doc = "Bits 0:2 - It's used to select the clock phase of the output signal from phase 0, phase 90, phase 180, phase 270."]
143 #[inline(always)]
144 #[must_use]
145 pub fn cclkin_edge_drv_sel(&mut self) -> CCLKIN_EDGE_DRV_SEL_W<CLK_EDGE_SEL_SPEC> {
146 CCLKIN_EDGE_DRV_SEL_W::new(self, 0)
147 }
148 #[doc = "Bits 3:5 - It's used to select the clock phase of the input signal from phase 0, phase 90, phase 180, phase 270."]
149 #[inline(always)]
150 #[must_use]
151 pub fn cclkin_edge_sam_sel(&mut self) -> CCLKIN_EDGE_SAM_SEL_W<CLK_EDGE_SEL_SPEC> {
152 CCLKIN_EDGE_SAM_SEL_W::new(self, 3)
153 }
154 #[doc = "Bits 6:8 - It's used to select the clock phase of the internal signal from phase 0, phase 90, phase 180, phase 270."]
155 #[inline(always)]
156 #[must_use]
157 pub fn cclkin_edge_slf_sel(&mut self) -> CCLKIN_EDGE_SLF_SEL_W<CLK_EDGE_SEL_SPEC> {
158 CCLKIN_EDGE_SLF_SEL_W::new(self, 6)
159 }
160 #[doc = "Bits 9:12 - The high level of the divider clock. The value should be smaller than CCLKIN_EDGE_L."]
161 #[inline(always)]
162 #[must_use]
163 pub fn ccllkin_edge_h(&mut self) -> CCLLKIN_EDGE_H_W<CLK_EDGE_SEL_SPEC> {
164 CCLLKIN_EDGE_H_W::new(self, 9)
165 }
166 #[doc = "Bits 13:16 - The low level of the divider clock. The value should be larger than CCLKIN_EDGE_H."]
167 #[inline(always)]
168 #[must_use]
169 pub fn ccllkin_edge_l(&mut self) -> CCLLKIN_EDGE_L_W<CLK_EDGE_SEL_SPEC> {
170 CCLLKIN_EDGE_L_W::new(self, 13)
171 }
172 #[doc = "Bits 17:20 - The clock division of cclk_in."]
173 #[inline(always)]
174 #[must_use]
175 pub fn ccllkin_edge_n(&mut self) -> CCLLKIN_EDGE_N_W<CLK_EDGE_SEL_SPEC> {
176 CCLLKIN_EDGE_N_W::new(self, 17)
177 }
178 #[doc = "Bit 21 - Enable esdio mode."]
179 #[inline(always)]
180 #[must_use]
181 pub fn esdio_mode(&mut self) -> ESDIO_MODE_W<CLK_EDGE_SEL_SPEC> {
182 ESDIO_MODE_W::new(self, 21)
183 }
184 #[doc = "Bit 22 - Enable esd mode."]
185 #[inline(always)]
186 #[must_use]
187 pub fn esd_mode(&mut self) -> ESD_MODE_W<CLK_EDGE_SEL_SPEC> {
188 ESD_MODE_W::new(self, 22)
189 }
190 #[doc = "Bit 23 - Sdio clock enable."]
191 #[inline(always)]
192 #[must_use]
193 pub fn cclk_en(&mut self) -> CCLK_EN_W<CLK_EDGE_SEL_SPEC> {
194 CCLK_EN_W::new(self, 23)
195 }
196 #[doc = "Bit 24 - Enable ultra high speed mode, use dll to generate clk."]
197 #[inline(always)]
198 #[must_use]
199 pub fn ultra_high_speed_mode(&mut self) -> ULTRA_HIGH_SPEED_MODE_W<CLK_EDGE_SEL_SPEC> {
200 ULTRA_HIGH_SPEED_MODE_W::new(self, 24)
201 }
202}
203#[doc = "SDIO control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clk_edge_sel::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clk_edge_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
204pub struct CLK_EDGE_SEL_SPEC;
205impl crate::RegisterSpec for CLK_EDGE_SEL_SPEC {
206 type Ux = u32;
207}
208#[doc = "`read()` method returns [`clk_edge_sel::R`](R) reader structure"]
209impl crate::Readable for CLK_EDGE_SEL_SPEC {}
210#[doc = "`write(|w| ..)` method takes [`clk_edge_sel::W`](W) writer structure"]
211impl crate::Writable for CLK_EDGE_SEL_SPEC {
212 type Safety = crate::Unsafe;
213 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
214 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
215}
216#[doc = "`reset()` method sets CLK_EDGE_SEL to value 0x0082_0200"]
217impl crate::Resettable for CLK_EDGE_SEL_SPEC {
218 const RESET_VALUE: u32 = 0x0082_0200;
219}