esp32p4/rmt/
rx_chconf0.rs

1#[doc = "Register `RX_CH%sCONF0` reader"]
2pub type R = crate::R<RX_CHCONF0_SPEC>;
3#[doc = "Register `RX_CH%sCONF0` writer"]
4pub type W = crate::W<RX_CHCONF0_SPEC>;
5#[doc = "Field `DIV_CNT_CH4` reader - This register is used to configure the divider for clock of CHANNEL%s."]
6pub type DIV_CNT_CH4_R = crate::FieldReader;
7#[doc = "Field `DIV_CNT_CH4` writer - This register is used to configure the divider for clock of CHANNEL%s."]
8pub type DIV_CNT_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `IDLE_THRES_CH4` reader - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
10pub type IDLE_THRES_CH4_R = crate::FieldReader<u16>;
11#[doc = "Field `IDLE_THRES_CH4` writer - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
12pub type IDLE_THRES_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 15, u16>;
13#[doc = "Field `MEM_SIZE_CH4` reader - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
14pub type MEM_SIZE_CH4_R = crate::FieldReader;
15#[doc = "Field `MEM_SIZE_CH4` writer - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
16pub type MEM_SIZE_CH4_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
17#[doc = "Field `CARRIER_EN_CH4` reader - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
18pub type CARRIER_EN_CH4_R = crate::BitReader;
19#[doc = "Field `CARRIER_EN_CH4` writer - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
20pub type CARRIER_EN_CH4_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CARRIER_OUT_LV_CH4` reader - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."]
22pub type CARRIER_OUT_LV_CH4_R = crate::BitReader;
23#[doc = "Field `CARRIER_OUT_LV_CH4` writer - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."]
24pub type CARRIER_OUT_LV_CH4_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
27    #[inline(always)]
28    pub fn div_cnt_ch4(&self) -> DIV_CNT_CH4_R {
29        DIV_CNT_CH4_R::new((self.bits & 0xff) as u8)
30    }
31    #[doc = "Bits 8:22 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
32    #[inline(always)]
33    pub fn idle_thres_ch4(&self) -> IDLE_THRES_CH4_R {
34        IDLE_THRES_CH4_R::new(((self.bits >> 8) & 0x7fff) as u16)
35    }
36    #[doc = "Bits 24:27 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
37    #[inline(always)]
38    pub fn mem_size_ch4(&self) -> MEM_SIZE_CH4_R {
39        MEM_SIZE_CH4_R::new(((self.bits >> 24) & 0x0f) as u8)
40    }
41    #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
42    #[inline(always)]
43    pub fn carrier_en_ch4(&self) -> CARRIER_EN_CH4_R {
44        CARRIER_EN_CH4_R::new(((self.bits >> 28) & 1) != 0)
45    }
46    #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."]
47    #[inline(always)]
48    pub fn carrier_out_lv_ch4(&self) -> CARRIER_OUT_LV_CH4_R {
49        CARRIER_OUT_LV_CH4_R::new(((self.bits >> 29) & 1) != 0)
50    }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55        f.debug_struct("RX_CHCONF0")
56            .field(
57                "div_cnt_ch4",
58                &format_args!("{}", self.div_cnt_ch4().bits()),
59            )
60            .field(
61                "idle_thres_ch4",
62                &format_args!("{}", self.idle_thres_ch4().bits()),
63            )
64            .field(
65                "mem_size_ch4",
66                &format_args!("{}", self.mem_size_ch4().bits()),
67            )
68            .field(
69                "carrier_en_ch4",
70                &format_args!("{}", self.carrier_en_ch4().bit()),
71            )
72            .field(
73                "carrier_out_lv_ch4",
74                &format_args!("{}", self.carrier_out_lv_ch4().bit()),
75            )
76            .finish()
77    }
78}
79#[cfg(feature = "impl-register-debug")]
80impl core::fmt::Debug for crate::generic::Reg<RX_CHCONF0_SPEC> {
81    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
82        core::fmt::Debug::fmt(&self.read(), f)
83    }
84}
85impl W {
86    #[doc = "Bits 0:7 - This register is used to configure the divider for clock of CHANNEL%s."]
87    #[inline(always)]
88    #[must_use]
89    pub fn div_cnt_ch4(&mut self) -> DIV_CNT_CH4_W<RX_CHCONF0_SPEC> {
90        DIV_CNT_CH4_W::new(self, 0)
91    }
92    #[doc = "Bits 8:22 - When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished."]
93    #[inline(always)]
94    #[must_use]
95    pub fn idle_thres_ch4(&mut self) -> IDLE_THRES_CH4_W<RX_CHCONF0_SPEC> {
96        IDLE_THRES_CH4_W::new(self, 8)
97    }
98    #[doc = "Bits 24:27 - This register is used to configure the maximum size of memory allocated to CHANNEL%s."]
99    #[inline(always)]
100    #[must_use]
101    pub fn mem_size_ch4(&mut self) -> MEM_SIZE_CH4_W<RX_CHCONF0_SPEC> {
102        MEM_SIZE_CH4_W::new(self, 24)
103    }
104    #[doc = "Bit 28 - This is the carrier modulation enable-control bit for CHANNEL%s. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out."]
105    #[inline(always)]
106    #[must_use]
107    pub fn carrier_en_ch4(&mut self) -> CARRIER_EN_CH4_W<RX_CHCONF0_SPEC> {
108        CARRIER_EN_CH4_W::new(self, 28)
109    }
110    #[doc = "Bit 29 - This bit is used to configure the position of carrier wave for CHANNEL%s.1'h0: add carrier wave on low level.1'h1: add carrier wave on high level."]
111    #[inline(always)]
112    #[must_use]
113    pub fn carrier_out_lv_ch4(&mut self) -> CARRIER_OUT_LV_CH4_W<RX_CHCONF0_SPEC> {
114        CARRIER_OUT_LV_CH4_W::new(self, 29)
115    }
116}
117#[doc = "Channel %s configure register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_chconf0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_chconf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
118pub struct RX_CHCONF0_SPEC;
119impl crate::RegisterSpec for RX_CHCONF0_SPEC {
120    type Ux = u32;
121}
122#[doc = "`read()` method returns [`rx_chconf0::R`](R) reader structure"]
123impl crate::Readable for RX_CHCONF0_SPEC {}
124#[doc = "`write(|w| ..)` method takes [`rx_chconf0::W`](W) writer structure"]
125impl crate::Writable for RX_CHCONF0_SPEC {
126    type Safety = crate::Unsafe;
127    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
128    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
129}
130#[doc = "`reset()` method sets RX_CH%sCONF0 to value 0x317f_ff02"]
131impl crate::Resettable for RX_CHCONF0_SPEC {
132    const RESET_VALUE: u32 = 0x317f_ff02;
133}
esp32p4/rmt/rx_chconf0.rs

esp32p4/rmt/
rx_chconf0.rs
