esp32p4/pau/
regdma_link_0_addr.rs1#[doc = "Register `REGDMA_LINK_0_ADDR` reader"]
2pub type R = crate::R<REGDMA_LINK_0_ADDR_SPEC>;
3#[doc = "Register `REGDMA_LINK_0_ADDR` writer"]
4pub type W = crate::W<REGDMA_LINK_0_ADDR_SPEC>;
5#[doc = "Field `LINK_ADDR_0` reader - link_0_addr reg"]
6pub type LINK_ADDR_0_R = crate::FieldReader<u32>;
7#[doc = "Field `LINK_ADDR_0` writer - link_0_addr reg"]
8pub type LINK_ADDR_0_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
9impl R {
10 #[doc = "Bits 0:31 - link_0_addr reg"]
11 #[inline(always)]
12 pub fn link_addr_0(&self) -> LINK_ADDR_0_R {
13 LINK_ADDR_0_R::new(self.bits)
14 }
15}
16#[cfg(feature = "impl-register-debug")]
17impl core::fmt::Debug for R {
18 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
19 f.debug_struct("REGDMA_LINK_0_ADDR")
20 .field(
21 "link_addr_0",
22 &format_args!("{}", self.link_addr_0().bits()),
23 )
24 .finish()
25 }
26}
27#[cfg(feature = "impl-register-debug")]
28impl core::fmt::Debug for crate::generic::Reg<REGDMA_LINK_0_ADDR_SPEC> {
29 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
30 core::fmt::Debug::fmt(&self.read(), f)
31 }
32}
33impl W {
34 #[doc = "Bits 0:31 - link_0_addr reg"]
35 #[inline(always)]
36 #[must_use]
37 pub fn link_addr_0(&mut self) -> LINK_ADDR_0_W<REGDMA_LINK_0_ADDR_SPEC> {
38 LINK_ADDR_0_W::new(self, 0)
39 }
40}
41#[doc = "link_0_addr\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`regdma_link_0_addr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`regdma_link_0_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
42pub struct REGDMA_LINK_0_ADDR_SPEC;
43impl crate::RegisterSpec for REGDMA_LINK_0_ADDR_SPEC {
44 type Ux = u32;
45}
46#[doc = "`read()` method returns [`regdma_link_0_addr::R`](R) reader structure"]
47impl crate::Readable for REGDMA_LINK_0_ADDR_SPEC {}
48#[doc = "`write(|w| ..)` method takes [`regdma_link_0_addr::W`](W) writer structure"]
49impl crate::Writable for REGDMA_LINK_0_ADDR_SPEC {
50 type Safety = crate::Unsafe;
51 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
52 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
53}
54#[doc = "`reset()` method sets REGDMA_LINK_0_ADDR to value 0"]
55impl crate::Resettable for REGDMA_LINK_0_ADDR_SPEC {
56 const RESET_VALUE: u32 = 0;
57}