esp32p4/parl_io/
rx_mode_cfg.rs1#[doc = "Register `RX_MODE_CFG` reader"]
2pub type R = crate::R<RX_MODE_CFG_SPEC>;
3#[doc = "Register `RX_MODE_CFG` writer"]
4pub type W = crate::W<RX_MODE_CFG_SPEC>;
5#[doc = "Field `RX_EXT_EN_SEL` reader - Configures rx external enable signal selection from IO PAD."]
6pub type RX_EXT_EN_SEL_R = crate::FieldReader;
7#[doc = "Field `RX_EXT_EN_SEL` writer - Configures rx external enable signal selection from IO PAD."]
8pub type RX_EXT_EN_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `RX_SW_EN` reader - Set this bit to enable data sampling by software."]
10pub type RX_SW_EN_R = crate::BitReader;
11#[doc = "Field `RX_SW_EN` writer - Set this bit to enable data sampling by software."]
12pub type RX_SW_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RX_EXT_EN_INV` reader - Set this bit to invert the external enable signal."]
14pub type RX_EXT_EN_INV_R = crate::BitReader;
15#[doc = "Field `RX_EXT_EN_INV` writer - Set this bit to invert the external enable signal."]
16pub type RX_EXT_EN_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `RX_PULSE_SUBMODE_SEL` reader - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"]
18pub type RX_PULSE_SUBMODE_SEL_R = crate::FieldReader;
19#[doc = "Field `RX_PULSE_SUBMODE_SEL` writer - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"]
20pub type RX_PULSE_SUBMODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
21#[doc = "Field `RX_SMP_MODE_SEL` reader - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"]
22pub type RX_SMP_MODE_SEL_R = crate::FieldReader;
23#[doc = "Field `RX_SMP_MODE_SEL` writer - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"]
24pub type RX_SMP_MODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
25impl R {
26 #[doc = "Bits 21:24 - Configures rx external enable signal selection from IO PAD."]
27 #[inline(always)]
28 pub fn rx_ext_en_sel(&self) -> RX_EXT_EN_SEL_R {
29 RX_EXT_EN_SEL_R::new(((self.bits >> 21) & 0x0f) as u8)
30 }
31 #[doc = "Bit 25 - Set this bit to enable data sampling by software."]
32 #[inline(always)]
33 pub fn rx_sw_en(&self) -> RX_SW_EN_R {
34 RX_SW_EN_R::new(((self.bits >> 25) & 1) != 0)
35 }
36 #[doc = "Bit 26 - Set this bit to invert the external enable signal."]
37 #[inline(always)]
38 pub fn rx_ext_en_inv(&self) -> RX_EXT_EN_INV_R {
39 RX_EXT_EN_INV_R::new(((self.bits >> 26) & 1) != 0)
40 }
41 #[doc = "Bits 27:29 - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"]
42 #[inline(always)]
43 pub fn rx_pulse_submode_sel(&self) -> RX_PULSE_SUBMODE_SEL_R {
44 RX_PULSE_SUBMODE_SEL_R::new(((self.bits >> 27) & 7) as u8)
45 }
46 #[doc = "Bits 30:31 - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"]
47 #[inline(always)]
48 pub fn rx_smp_mode_sel(&self) -> RX_SMP_MODE_SEL_R {
49 RX_SMP_MODE_SEL_R::new(((self.bits >> 30) & 3) as u8)
50 }
51}
52#[cfg(feature = "impl-register-debug")]
53impl core::fmt::Debug for R {
54 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
55 f.debug_struct("RX_MODE_CFG")
56 .field(
57 "rx_ext_en_sel",
58 &format_args!("{}", self.rx_ext_en_sel().bits()),
59 )
60 .field("rx_sw_en", &format_args!("{}", self.rx_sw_en().bit()))
61 .field(
62 "rx_ext_en_inv",
63 &format_args!("{}", self.rx_ext_en_inv().bit()),
64 )
65 .field(
66 "rx_pulse_submode_sel",
67 &format_args!("{}", self.rx_pulse_submode_sel().bits()),
68 )
69 .field(
70 "rx_smp_mode_sel",
71 &format_args!("{}", self.rx_smp_mode_sel().bits()),
72 )
73 .finish()
74 }
75}
76#[cfg(feature = "impl-register-debug")]
77impl core::fmt::Debug for crate::generic::Reg<RX_MODE_CFG_SPEC> {
78 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
79 core::fmt::Debug::fmt(&self.read(), f)
80 }
81}
82impl W {
83 #[doc = "Bits 21:24 - Configures rx external enable signal selection from IO PAD."]
84 #[inline(always)]
85 #[must_use]
86 pub fn rx_ext_en_sel(&mut self) -> RX_EXT_EN_SEL_W<RX_MODE_CFG_SPEC> {
87 RX_EXT_EN_SEL_W::new(self, 21)
88 }
89 #[doc = "Bit 25 - Set this bit to enable data sampling by software."]
90 #[inline(always)]
91 #[must_use]
92 pub fn rx_sw_en(&mut self) -> RX_SW_EN_W<RX_MODE_CFG_SPEC> {
93 RX_SW_EN_W::new(self, 25)
94 }
95 #[doc = "Bit 26 - Set this bit to invert the external enable signal."]
96 #[inline(always)]
97 #[must_use]
98 pub fn rx_ext_en_inv(&mut self) -> RX_EXT_EN_INV_W<RX_MODE_CFG_SPEC> {
99 RX_EXT_EN_INV_W::new(self, 26)
100 }
101 #[doc = "Bits 27:29 - Configures the rxd pulse sampling submode. 4'd0: positive pulse start(data bit included) && positive pulse end(data bit included) 4'd1: positive pulse start(data bit included) && positive pulse end (data bit excluded) 4'd2: positive pulse start(data bit excluded) && positive pulse end (data bit included) 4'd3: positive pulse start(data bit excluded) && positive pulse end (data bit excluded) 4'd4: positive pulse start(data bit included) && length end 4'd5: positive pulse start(data bit excluded) && length end"]
102 #[inline(always)]
103 #[must_use]
104 pub fn rx_pulse_submode_sel(&mut self) -> RX_PULSE_SUBMODE_SEL_W<RX_MODE_CFG_SPEC> {
105 RX_PULSE_SUBMODE_SEL_W::new(self, 27)
106 }
107 #[doc = "Bits 30:31 - Configures the rxd sampling mode. 2'b00: external level enable mode 2'b01: external pulse enable mode 2'b10: internal software enable mode"]
108 #[inline(always)]
109 #[must_use]
110 pub fn rx_smp_mode_sel(&mut self) -> RX_SMP_MODE_SEL_W<RX_MODE_CFG_SPEC> {
111 RX_SMP_MODE_SEL_W::new(self, 30)
112 }
113}
114#[doc = "Parallel RX Sampling mode configuration register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rx_mode_cfg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rx_mode_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct RX_MODE_CFG_SPEC;
116impl crate::RegisterSpec for RX_MODE_CFG_SPEC {
117 type Ux = u32;
118}
119#[doc = "`read()` method returns [`rx_mode_cfg::R`](R) reader structure"]
120impl crate::Readable for RX_MODE_CFG_SPEC {}
121#[doc = "`write(|w| ..)` method takes [`rx_mode_cfg::W`](W) writer structure"]
122impl crate::Writable for RX_MODE_CFG_SPEC {
123 type Safety = crate::Unsafe;
124 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
125 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
126}
127#[doc = "`reset()` method sets RX_MODE_CFG to value 0x00e0_0000"]
128impl crate::Resettable for RX_MODE_CFG_SPEC {
129 const RESET_VALUE: u32 = 0x00e0_0000;
130}