esp32p4/parl_io/
int_raw.rs1#[doc = "Register `INT_RAW` reader"]
2pub type R = crate::R<INT_RAW_SPEC>;
3#[doc = "Register `INT_RAW` writer"]
4pub type W = crate::W<INT_RAW_SPEC>;
5#[doc = "Field `TX_FIFO_REMPTY` reader - The raw interrupt status of TX_FIFO_REMPTY_INT."]
6pub type TX_FIFO_REMPTY_R = crate::BitReader;
7#[doc = "Field `TX_FIFO_REMPTY` writer - The raw interrupt status of TX_FIFO_REMPTY_INT."]
8pub type TX_FIFO_REMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `RX_FIFO_WOVF` reader - The raw interrupt status of RX_FIFO_WOVF_INT."]
10pub type RX_FIFO_WOVF_R = crate::BitReader;
11#[doc = "Field `RX_FIFO_WOVF` writer - The raw interrupt status of RX_FIFO_WOVF_INT."]
12pub type RX_FIFO_WOVF_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `TX_EOF` reader - The raw interrupt status of TX_EOF_INT."]
14pub type TX_EOF_R = crate::BitReader;
15#[doc = "Field `TX_EOF` writer - The raw interrupt status of TX_EOF_INT."]
16pub type TX_EOF_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18 #[doc = "Bit 0 - The raw interrupt status of TX_FIFO_REMPTY_INT."]
19 #[inline(always)]
20 pub fn tx_fifo_rempty(&self) -> TX_FIFO_REMPTY_R {
21 TX_FIFO_REMPTY_R::new((self.bits & 1) != 0)
22 }
23 #[doc = "Bit 1 - The raw interrupt status of RX_FIFO_WOVF_INT."]
24 #[inline(always)]
25 pub fn rx_fifo_wovf(&self) -> RX_FIFO_WOVF_R {
26 RX_FIFO_WOVF_R::new(((self.bits >> 1) & 1) != 0)
27 }
28 #[doc = "Bit 2 - The raw interrupt status of TX_EOF_INT."]
29 #[inline(always)]
30 pub fn tx_eof(&self) -> TX_EOF_R {
31 TX_EOF_R::new(((self.bits >> 2) & 1) != 0)
32 }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37 f.debug_struct("INT_RAW")
38 .field(
39 "tx_fifo_rempty",
40 &format_args!("{}", self.tx_fifo_rempty().bit()),
41 )
42 .field(
43 "rx_fifo_wovf",
44 &format_args!("{}", self.rx_fifo_wovf().bit()),
45 )
46 .field("tx_eof", &format_args!("{}", self.tx_eof().bit()))
47 .finish()
48 }
49}
50#[cfg(feature = "impl-register-debug")]
51impl core::fmt::Debug for crate::generic::Reg<INT_RAW_SPEC> {
52 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
53 core::fmt::Debug::fmt(&self.read(), f)
54 }
55}
56impl W {
57 #[doc = "Bit 0 - The raw interrupt status of TX_FIFO_REMPTY_INT."]
58 #[inline(always)]
59 #[must_use]
60 pub fn tx_fifo_rempty(&mut self) -> TX_FIFO_REMPTY_W<INT_RAW_SPEC> {
61 TX_FIFO_REMPTY_W::new(self, 0)
62 }
63 #[doc = "Bit 1 - The raw interrupt status of RX_FIFO_WOVF_INT."]
64 #[inline(always)]
65 #[must_use]
66 pub fn rx_fifo_wovf(&mut self) -> RX_FIFO_WOVF_W<INT_RAW_SPEC> {
67 RX_FIFO_WOVF_W::new(self, 1)
68 }
69 #[doc = "Bit 2 - The raw interrupt status of TX_EOF_INT."]
70 #[inline(always)]
71 #[must_use]
72 pub fn tx_eof(&mut self) -> TX_EOF_W<INT_RAW_SPEC> {
73 TX_EOF_W::new(self, 2)
74 }
75}
76#[doc = "Parallel IO interrupt raw singal status register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_raw::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_raw::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
77pub struct INT_RAW_SPEC;
78impl crate::RegisterSpec for INT_RAW_SPEC {
79 type Ux = u32;
80}
81#[doc = "`read()` method returns [`int_raw::R`](R) reader structure"]
82impl crate::Readable for INT_RAW_SPEC {}
83#[doc = "`write(|w| ..)` method takes [`int_raw::W`](W) writer structure"]
84impl crate::Writable for INT_RAW_SPEC {
85 type Safety = crate::Unsafe;
86 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
87 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
88}
89#[doc = "`reset()` method sets INT_RAW to value 0"]
90impl crate::Resettable for INT_RAW_SPEC {
91 const RESET_VALUE: u32 = 0;
92}