esp32p4/lp_i2s0/
lc_hung_conf.rs

1#[doc = "Register `LC_HUNG_CONF` reader"]
2pub type R = crate::R<LC_HUNG_CONF_SPEC>;
3#[doc = "Register `LC_HUNG_CONF` writer"]
4pub type W = crate::W<LC_HUNG_CONF_SPEC>;
5#[doc = "Field `LC_FIFO_TIMEOUT` reader - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
6pub type LC_FIFO_TIMEOUT_R = crate::FieldReader;
7#[doc = "Field `LC_FIFO_TIMEOUT` writer - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
8pub type LC_FIFO_TIMEOUT_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` reader - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
10pub type LC_FIFO_TIMEOUT_SHIFT_R = crate::FieldReader;
11#[doc = "Field `LC_FIFO_TIMEOUT_SHIFT` writer - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
12pub type LC_FIFO_TIMEOUT_SHIFT_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `LC_FIFO_TIMEOUT_ENA` reader - The enable bit for FIFO timeout"]
14pub type LC_FIFO_TIMEOUT_ENA_R = crate::BitReader;
15#[doc = "Field `LC_FIFO_TIMEOUT_ENA` writer - The enable bit for FIFO timeout"]
16pub type LC_FIFO_TIMEOUT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17impl R {
18    #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
19    #[inline(always)]
20    pub fn lc_fifo_timeout(&self) -> LC_FIFO_TIMEOUT_R {
21        LC_FIFO_TIMEOUT_R::new((self.bits & 0xff) as u8)
22    }
23    #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
24    #[inline(always)]
25    pub fn lc_fifo_timeout_shift(&self) -> LC_FIFO_TIMEOUT_SHIFT_R {
26        LC_FIFO_TIMEOUT_SHIFT_R::new(((self.bits >> 8) & 7) as u8)
27    }
28    #[doc = "Bit 11 - The enable bit for FIFO timeout"]
29    #[inline(always)]
30    pub fn lc_fifo_timeout_ena(&self) -> LC_FIFO_TIMEOUT_ENA_R {
31        LC_FIFO_TIMEOUT_ENA_R::new(((self.bits >> 11) & 1) != 0)
32    }
33}
34#[cfg(feature = "impl-register-debug")]
35impl core::fmt::Debug for R {
36    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
37        f.debug_struct("LC_HUNG_CONF")
38            .field(
39                "lc_fifo_timeout",
40                &format_args!("{}", self.lc_fifo_timeout().bits()),
41            )
42            .field(
43                "lc_fifo_timeout_shift",
44                &format_args!("{}", self.lc_fifo_timeout_shift().bits()),
45            )
46            .field(
47                "lc_fifo_timeout_ena",
48                &format_args!("{}", self.lc_fifo_timeout_ena().bit()),
49            )
50            .finish()
51    }
52}
53#[cfg(feature = "impl-register-debug")]
54impl core::fmt::Debug for crate::generic::Reg<LC_HUNG_CONF_SPEC> {
55    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
56        core::fmt::Debug::fmt(&self.read(), f)
57    }
58}
59impl W {
60    #[doc = "Bits 0:7 - the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value"]
61    #[inline(always)]
62    #[must_use]
63    pub fn lc_fifo_timeout(&mut self) -> LC_FIFO_TIMEOUT_W<LC_HUNG_CONF_SPEC> {
64        LC_FIFO_TIMEOUT_W::new(self, 0)
65    }
66    #[doc = "Bits 8:10 - The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift"]
67    #[inline(always)]
68    #[must_use]
69    pub fn lc_fifo_timeout_shift(&mut self) -> LC_FIFO_TIMEOUT_SHIFT_W<LC_HUNG_CONF_SPEC> {
70        LC_FIFO_TIMEOUT_SHIFT_W::new(self, 8)
71    }
72    #[doc = "Bit 11 - The enable bit for FIFO timeout"]
73    #[inline(always)]
74    #[must_use]
75    pub fn lc_fifo_timeout_ena(&mut self) -> LC_FIFO_TIMEOUT_ENA_W<LC_HUNG_CONF_SPEC> {
76        LC_FIFO_TIMEOUT_ENA_W::new(self, 11)
77    }
78}
79#[doc = "I2S HUNG configure register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lc_hung_conf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lc_hung_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
80pub struct LC_HUNG_CONF_SPEC;
81impl crate::RegisterSpec for LC_HUNG_CONF_SPEC {
82    type Ux = u32;
83}
84#[doc = "`read()` method returns [`lc_hung_conf::R`](R) reader structure"]
85impl crate::Readable for LC_HUNG_CONF_SPEC {}
86#[doc = "`write(|w| ..)` method takes [`lc_hung_conf::W`](W) writer structure"]
87impl crate::Writable for LC_HUNG_CONF_SPEC {
88    type Safety = crate::Unsafe;
89    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
90    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
91}
92#[doc = "`reset()` method sets LC_HUNG_CONF to value 0x0810"]
93impl crate::Resettable for LC_HUNG_CONF_SPEC {
94    const RESET_VALUE: u32 = 0x0810;
95}
esp32p4/lp_i2s0/lc_hung_conf.rs

esp32p4/lp_i2s0/
lc_hung_conf.rs
