1#[doc = "Register `LP_AONCLKRST_HPCPU_RESET_CTRL0` reader"]
2pub type R = crate::R<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC>;
3#[doc = "Register `LP_AONCLKRST_HPCPU_RESET_CTRL0` writer"]
4pub type W = crate::W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC>;
5#[doc = "Field `LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN` reader - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"]
6pub type LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_R = crate::BitReader;
7#[doc = "Field `LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN` writer - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"]
8pub type LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH` reader - need_des"]
10pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_R = crate::FieldReader;
11#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH` writer - need_des"]
12pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
13#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN` reader - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"]
14pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_R = crate::BitReader;
15#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN` writer - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"]
16pub type LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_WAIT` reader - need_des"]
18pub type LP_AONCLKRST_HPCORE0_STALL_WAIT_R = crate::FieldReader;
19#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_WAIT` writer - need_des"]
20pub type LP_AONCLKRST_HPCORE0_STALL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
21#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_EN` reader - need_des"]
22pub type LP_AONCLKRST_HPCORE0_STALL_EN_R = crate::BitReader;
23#[doc = "Field `LP_AONCLKRST_HPCORE0_STALL_EN` writer - need_des"]
24pub type LP_AONCLKRST_HPCORE0_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `LP_AONCLKRST_HPCORE0_SW_RESET` writer - need_des"]
26pub type LP_AONCLKRST_HPCORE0_SW_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
27#[doc = "Field `LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET` reader - need_des"]
28pub type LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_R = crate::BitReader;
29#[doc = "Field `LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET` writer - need_des"]
30pub type LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
31#[doc = "Field `LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL` reader - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
32pub type LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_R = crate::BitReader;
33#[doc = "Field `LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL` writer - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
34pub type LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
35#[doc = "Field `LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN` reader - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"]
36pub type LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_R = crate::BitReader;
37#[doc = "Field `LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN` writer - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"]
38pub type LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
39#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH` reader - need_des"]
40pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_R = crate::FieldReader;
41#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH` writer - need_des"]
42pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
43#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN` reader - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"]
44pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_R = crate::BitReader;
45#[doc = "Field `LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN` writer - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"]
46pub type LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
47#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_WAIT` reader - need_des"]
48pub type LP_AONCLKRST_HPCORE1_STALL_WAIT_R = crate::FieldReader;
49#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_WAIT` writer - need_des"]
50pub type LP_AONCLKRST_HPCORE1_STALL_WAIT_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
51#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_EN` reader - need_des"]
52pub type LP_AONCLKRST_HPCORE1_STALL_EN_R = crate::BitReader;
53#[doc = "Field `LP_AONCLKRST_HPCORE1_STALL_EN` writer - need_des"]
54pub type LP_AONCLKRST_HPCORE1_STALL_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
55#[doc = "Field `LP_AONCLKRST_HPCORE1_SW_RESET` writer - need_des"]
56pub type LP_AONCLKRST_HPCORE1_SW_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET` reader - need_des"]
58pub type LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_R = crate::BitReader;
59#[doc = "Field `LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET` writer - need_des"]
60pub type LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL` reader - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
62pub type LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_R = crate::BitReader;
63#[doc = "Field `LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL` writer - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
64pub type LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
65impl R {
66 #[doc = "Bit 0 - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"]
67 #[inline(always)]
68 pub fn lp_aonclkrst_hpcore0_lockup_reset_en(&self) -> LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_R {
69 LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_R::new((self.bits & 1) != 0)
70 }
71 #[doc = "Bits 1:3 - need_des"]
72 #[inline(always)]
73 pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_length(
74 &self,
75 ) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_R {
76 LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_R::new(((self.bits >> 1) & 7) as u8)
77 }
78 #[doc = "Bit 4 - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"]
79 #[inline(always)]
80 pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_en(&self) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_R {
81 LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_R::new(((self.bits >> 4) & 1) != 0)
82 }
83 #[doc = "Bits 5:11 - need_des"]
84 #[inline(always)]
85 pub fn lp_aonclkrst_hpcore0_stall_wait(&self) -> LP_AONCLKRST_HPCORE0_STALL_WAIT_R {
86 LP_AONCLKRST_HPCORE0_STALL_WAIT_R::new(((self.bits >> 5) & 0x7f) as u8)
87 }
88 #[doc = "Bit 12 - need_des"]
89 #[inline(always)]
90 pub fn lp_aonclkrst_hpcore0_stall_en(&self) -> LP_AONCLKRST_HPCORE0_STALL_EN_R {
91 LP_AONCLKRST_HPCORE0_STALL_EN_R::new(((self.bits >> 12) & 1) != 0)
92 }
93 #[doc = "Bit 14 - need_des"]
94 #[inline(always)]
95 pub fn lp_aonclkrst_hpcore0_ocd_halt_on_reset(
96 &self,
97 ) -> LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_R {
98 LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_R::new(((self.bits >> 14) & 1) != 0)
99 }
100 #[doc = "Bit 15 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
101 #[inline(always)]
102 pub fn lp_aonclkrst_hpcore0_stat_vector_sel(&self) -> LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_R {
103 LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_R::new(((self.bits >> 15) & 1) != 0)
104 }
105 #[doc = "Bit 16 - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"]
106 #[inline(always)]
107 pub fn lp_aonclkrst_hpcore1_lockup_reset_en(&self) -> LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_R {
108 LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_R::new(((self.bits >> 16) & 1) != 0)
109 }
110 #[doc = "Bits 17:19 - need_des"]
111 #[inline(always)]
112 pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_length(
113 &self,
114 ) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_R {
115 LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_R::new(((self.bits >> 17) & 7) as u8)
116 }
117 #[doc = "Bit 20 - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"]
118 #[inline(always)]
119 pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_en(&self) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_R {
120 LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_R::new(((self.bits >> 20) & 1) != 0)
121 }
122 #[doc = "Bits 21:27 - need_des"]
123 #[inline(always)]
124 pub fn lp_aonclkrst_hpcore1_stall_wait(&self) -> LP_AONCLKRST_HPCORE1_STALL_WAIT_R {
125 LP_AONCLKRST_HPCORE1_STALL_WAIT_R::new(((self.bits >> 21) & 0x7f) as u8)
126 }
127 #[doc = "Bit 28 - need_des"]
128 #[inline(always)]
129 pub fn lp_aonclkrst_hpcore1_stall_en(&self) -> LP_AONCLKRST_HPCORE1_STALL_EN_R {
130 LP_AONCLKRST_HPCORE1_STALL_EN_R::new(((self.bits >> 28) & 1) != 0)
131 }
132 #[doc = "Bit 30 - need_des"]
133 #[inline(always)]
134 pub fn lp_aonclkrst_hpcore1_ocd_halt_on_reset(
135 &self,
136 ) -> LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_R {
137 LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_R::new(((self.bits >> 30) & 1) != 0)
138 }
139 #[doc = "Bit 31 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
140 #[inline(always)]
141 pub fn lp_aonclkrst_hpcore1_stat_vector_sel(&self) -> LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_R {
142 LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_R::new(((self.bits >> 31) & 1) != 0)
143 }
144}
145#[cfg(feature = "impl-register-debug")]
146impl core::fmt::Debug for R {
147 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
148 f.debug_struct("LP_AONCLKRST_HPCPU_RESET_CTRL0")
149 .field(
150 "lp_aonclkrst_hpcore0_lockup_reset_en",
151 &format_args!("{}", self.lp_aonclkrst_hpcore0_lockup_reset_en().bit()),
152 )
153 .field(
154 "lp_aonclkrst_lp_wdt_hpcore0_reset_length",
155 &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore0_reset_length().bits()),
156 )
157 .field(
158 "lp_aonclkrst_lp_wdt_hpcore0_reset_en",
159 &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore0_reset_en().bit()),
160 )
161 .field(
162 "lp_aonclkrst_hpcore0_stall_wait",
163 &format_args!("{}", self.lp_aonclkrst_hpcore0_stall_wait().bits()),
164 )
165 .field(
166 "lp_aonclkrst_hpcore0_stall_en",
167 &format_args!("{}", self.lp_aonclkrst_hpcore0_stall_en().bit()),
168 )
169 .field(
170 "lp_aonclkrst_hpcore0_ocd_halt_on_reset",
171 &format_args!("{}", self.lp_aonclkrst_hpcore0_ocd_halt_on_reset().bit()),
172 )
173 .field(
174 "lp_aonclkrst_hpcore0_stat_vector_sel",
175 &format_args!("{}", self.lp_aonclkrst_hpcore0_stat_vector_sel().bit()),
176 )
177 .field(
178 "lp_aonclkrst_hpcore1_lockup_reset_en",
179 &format_args!("{}", self.lp_aonclkrst_hpcore1_lockup_reset_en().bit()),
180 )
181 .field(
182 "lp_aonclkrst_lp_wdt_hpcore1_reset_length",
183 &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore1_reset_length().bits()),
184 )
185 .field(
186 "lp_aonclkrst_lp_wdt_hpcore1_reset_en",
187 &format_args!("{}", self.lp_aonclkrst_lp_wdt_hpcore1_reset_en().bit()),
188 )
189 .field(
190 "lp_aonclkrst_hpcore1_stall_wait",
191 &format_args!("{}", self.lp_aonclkrst_hpcore1_stall_wait().bits()),
192 )
193 .field(
194 "lp_aonclkrst_hpcore1_stall_en",
195 &format_args!("{}", self.lp_aonclkrst_hpcore1_stall_en().bit()),
196 )
197 .field(
198 "lp_aonclkrst_hpcore1_ocd_halt_on_reset",
199 &format_args!("{}", self.lp_aonclkrst_hpcore1_ocd_halt_on_reset().bit()),
200 )
201 .field(
202 "lp_aonclkrst_hpcore1_stat_vector_sel",
203 &format_args!("{}", self.lp_aonclkrst_hpcore1_stat_vector_sel().bit()),
204 )
205 .finish()
206 }
207}
208#[cfg(feature = "impl-register-debug")]
209impl core::fmt::Debug for crate::generic::Reg<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
210 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
211 core::fmt::Debug::fmt(&self.read(), f)
212 }
213}
214impl W {
215 #[doc = "Bit 0 - write 1 to enable hpcore0 lockup reset feature, write 0 to disable hpcore0 lockup reset feature"]
216 #[inline(always)]
217 #[must_use]
218 pub fn lp_aonclkrst_hpcore0_lockup_reset_en(
219 &mut self,
220 ) -> LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
221 LP_AONCLKRST_HPCORE0_LOCKUP_RESET_EN_W::new(self, 0)
222 }
223 #[doc = "Bits 1:3 - need_des"]
224 #[inline(always)]
225 #[must_use]
226 pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_length(
227 &mut self,
228 ) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
229 LP_AONCLKRST_LP_WDT_HPCORE0_RESET_LENGTH_W::new(self, 1)
230 }
231 #[doc = "Bit 4 - write 1 to enable lp_wdt reset hpcore0 feature, write 0 to disable lp_wdt reset hpcore0 feature"]
232 #[inline(always)]
233 #[must_use]
234 pub fn lp_aonclkrst_lp_wdt_hpcore0_reset_en(
235 &mut self,
236 ) -> LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
237 LP_AONCLKRST_LP_WDT_HPCORE0_RESET_EN_W::new(self, 4)
238 }
239 #[doc = "Bits 5:11 - need_des"]
240 #[inline(always)]
241 #[must_use]
242 pub fn lp_aonclkrst_hpcore0_stall_wait(
243 &mut self,
244 ) -> LP_AONCLKRST_HPCORE0_STALL_WAIT_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
245 LP_AONCLKRST_HPCORE0_STALL_WAIT_W::new(self, 5)
246 }
247 #[doc = "Bit 12 - need_des"]
248 #[inline(always)]
249 #[must_use]
250 pub fn lp_aonclkrst_hpcore0_stall_en(
251 &mut self,
252 ) -> LP_AONCLKRST_HPCORE0_STALL_EN_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
253 LP_AONCLKRST_HPCORE0_STALL_EN_W::new(self, 12)
254 }
255 #[doc = "Bit 13 - need_des"]
256 #[inline(always)]
257 #[must_use]
258 pub fn lp_aonclkrst_hpcore0_sw_reset(
259 &mut self,
260 ) -> LP_AONCLKRST_HPCORE0_SW_RESET_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
261 LP_AONCLKRST_HPCORE0_SW_RESET_W::new(self, 13)
262 }
263 #[doc = "Bit 14 - need_des"]
264 #[inline(always)]
265 #[must_use]
266 pub fn lp_aonclkrst_hpcore0_ocd_halt_on_reset(
267 &mut self,
268 ) -> LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
269 LP_AONCLKRST_HPCORE0_OCD_HALT_ON_RESET_W::new(self, 14)
270 }
271 #[doc = "Bit 15 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
272 #[inline(always)]
273 #[must_use]
274 pub fn lp_aonclkrst_hpcore0_stat_vector_sel(
275 &mut self,
276 ) -> LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
277 LP_AONCLKRST_HPCORE0_STAT_VECTOR_SEL_W::new(self, 15)
278 }
279 #[doc = "Bit 16 - write 1 to enable hpcore1 lockup reset feature, write 0 to disable hpcore1 lockup reset feature"]
280 #[inline(always)]
281 #[must_use]
282 pub fn lp_aonclkrst_hpcore1_lockup_reset_en(
283 &mut self,
284 ) -> LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
285 LP_AONCLKRST_HPCORE1_LOCKUP_RESET_EN_W::new(self, 16)
286 }
287 #[doc = "Bits 17:19 - need_des"]
288 #[inline(always)]
289 #[must_use]
290 pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_length(
291 &mut self,
292 ) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
293 LP_AONCLKRST_LP_WDT_HPCORE1_RESET_LENGTH_W::new(self, 17)
294 }
295 #[doc = "Bit 20 - write 1 to enable lp_wdt reset hpcore1 feature, write 0 to disable lp_wdt reset hpcore1 feature"]
296 #[inline(always)]
297 #[must_use]
298 pub fn lp_aonclkrst_lp_wdt_hpcore1_reset_en(
299 &mut self,
300 ) -> LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
301 LP_AONCLKRST_LP_WDT_HPCORE1_RESET_EN_W::new(self, 20)
302 }
303 #[doc = "Bits 21:27 - need_des"]
304 #[inline(always)]
305 #[must_use]
306 pub fn lp_aonclkrst_hpcore1_stall_wait(
307 &mut self,
308 ) -> LP_AONCLKRST_HPCORE1_STALL_WAIT_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
309 LP_AONCLKRST_HPCORE1_STALL_WAIT_W::new(self, 21)
310 }
311 #[doc = "Bit 28 - need_des"]
312 #[inline(always)]
313 #[must_use]
314 pub fn lp_aonclkrst_hpcore1_stall_en(
315 &mut self,
316 ) -> LP_AONCLKRST_HPCORE1_STALL_EN_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
317 LP_AONCLKRST_HPCORE1_STALL_EN_W::new(self, 28)
318 }
319 #[doc = "Bit 29 - need_des"]
320 #[inline(always)]
321 #[must_use]
322 pub fn lp_aonclkrst_hpcore1_sw_reset(
323 &mut self,
324 ) -> LP_AONCLKRST_HPCORE1_SW_RESET_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
325 LP_AONCLKRST_HPCORE1_SW_RESET_W::new(self, 29)
326 }
327 #[doc = "Bit 30 - need_des"]
328 #[inline(always)]
329 #[must_use]
330 pub fn lp_aonclkrst_hpcore1_ocd_halt_on_reset(
331 &mut self,
332 ) -> LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
333 LP_AONCLKRST_HPCORE1_OCD_HALT_ON_RESET_W::new(self, 30)
334 }
335 #[doc = "Bit 31 - 1'b1: boot from HP TCM ROM: 0x4FC00000 1'b0: boot from LP TCM RAM: 0x50108000"]
336 #[inline(always)]
337 #[must_use]
338 pub fn lp_aonclkrst_hpcore1_stat_vector_sel(
339 &mut self,
340 ) -> LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_W<LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC> {
341 LP_AONCLKRST_HPCORE1_STAT_VECTOR_SEL_W::new(self, 31)
342 }
343}
344#[doc = "need_des\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`lp_aonclkrst_hpcpu_reset_ctrl0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`lp_aonclkrst_hpcpu_reset_ctrl0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
345pub struct LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC;
346impl crate::RegisterSpec for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC {
347 type Ux = u32;
348}
349#[doc = "`read()` method returns [`lp_aonclkrst_hpcpu_reset_ctrl0::R`](R) reader structure"]
350impl crate::Readable for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC {}
351#[doc = "`write(|w| ..)` method takes [`lp_aonclkrst_hpcpu_reset_ctrl0::W`](W) writer structure"]
352impl crate::Writable for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC {
353 type Safety = crate::Unsafe;
354 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
355 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
356}
357#[doc = "`reset()` method sets LP_AONCLKRST_HPCPU_RESET_CTRL0 to value 0x8002_8002"]
358impl crate::Resettable for LP_AONCLKRST_HPCPU_RESET_CTRL0_SPEC {
359 const RESET_VALUE: u32 = 0x8002_8002;
360}