esp32p4/lp_adc/
int_ena.rs

1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `COCPU_SARADC1_INT_ENA` reader - ADC1 Conversion is done, int enable."]
6pub type COCPU_SARADC1_INT_ENA_R = crate::BitReader;
7#[doc = "Field `COCPU_SARADC1_INT_ENA` writer - ADC1 Conversion is done, int enable."]
8pub type COCPU_SARADC1_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `COCPU_SARADC2_INT_ENA` reader - ADC2 Conversion is done, int enable."]
10pub type COCPU_SARADC2_INT_ENA_R = crate::BitReader;
11#[doc = "Field `COCPU_SARADC2_INT_ENA` writer - ADC2 Conversion is done, int enable."]
12pub type COCPU_SARADC2_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `COCPU_SARADC1_ERROR_INT_ENA` reader - An errro occurs from ADC1, int enable."]
14pub type COCPU_SARADC1_ERROR_INT_ENA_R = crate::BitReader;
15#[doc = "Field `COCPU_SARADC1_ERROR_INT_ENA` writer - An errro occurs from ADC1, int enable."]
16pub type COCPU_SARADC1_ERROR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `COCPU_SARADC2_ERROR_INT_ENA` reader - An errro occurs from ADC2, int enable."]
18pub type COCPU_SARADC2_ERROR_INT_ENA_R = crate::BitReader;
19#[doc = "Field `COCPU_SARADC2_ERROR_INT_ENA` writer - An errro occurs from ADC2, int enable."]
20pub type COCPU_SARADC2_ERROR_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `COCPU_SARADC1_WAKE_INT_ENA` reader - A wakeup event is triggered from ADC1, int enable."]
22pub type COCPU_SARADC1_WAKE_INT_ENA_R = crate::BitReader;
23#[doc = "Field `COCPU_SARADC1_WAKE_INT_ENA` writer - A wakeup event is triggered from ADC1, int enable."]
24pub type COCPU_SARADC1_WAKE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `COCPU_SARADC2_WAKE_INT_ENA` reader - A wakeup event is triggered from ADC2, int enable."]
26pub type COCPU_SARADC2_WAKE_INT_ENA_R = crate::BitReader;
27#[doc = "Field `COCPU_SARADC2_WAKE_INT_ENA` writer - A wakeup event is triggered from ADC2, int enable."]
28pub type COCPU_SARADC2_WAKE_INT_ENA_W<'a, REG> = crate::BitWriter<'a, REG>;
29impl R {
30    #[doc = "Bit 0 - ADC1 Conversion is done, int enable."]
31    #[inline(always)]
32    pub fn cocpu_saradc1_int_ena(&self) -> COCPU_SARADC1_INT_ENA_R {
33        COCPU_SARADC1_INT_ENA_R::new((self.bits & 1) != 0)
34    }
35    #[doc = "Bit 1 - ADC2 Conversion is done, int enable."]
36    #[inline(always)]
37    pub fn cocpu_saradc2_int_ena(&self) -> COCPU_SARADC2_INT_ENA_R {
38        COCPU_SARADC2_INT_ENA_R::new(((self.bits >> 1) & 1) != 0)
39    }
40    #[doc = "Bit 2 - An errro occurs from ADC1, int enable."]
41    #[inline(always)]
42    pub fn cocpu_saradc1_error_int_ena(&self) -> COCPU_SARADC1_ERROR_INT_ENA_R {
43        COCPU_SARADC1_ERROR_INT_ENA_R::new(((self.bits >> 2) & 1) != 0)
44    }
45    #[doc = "Bit 3 - An errro occurs from ADC2, int enable."]
46    #[inline(always)]
47    pub fn cocpu_saradc2_error_int_ena(&self) -> COCPU_SARADC2_ERROR_INT_ENA_R {
48        COCPU_SARADC2_ERROR_INT_ENA_R::new(((self.bits >> 3) & 1) != 0)
49    }
50    #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int enable."]
51    #[inline(always)]
52    pub fn cocpu_saradc1_wake_int_ena(&self) -> COCPU_SARADC1_WAKE_INT_ENA_R {
53        COCPU_SARADC1_WAKE_INT_ENA_R::new(((self.bits >> 4) & 1) != 0)
54    }
55    #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int enable."]
56    #[inline(always)]
57    pub fn cocpu_saradc2_wake_int_ena(&self) -> COCPU_SARADC2_WAKE_INT_ENA_R {
58        COCPU_SARADC2_WAKE_INT_ENA_R::new(((self.bits >> 5) & 1) != 0)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("INT_ENA")
65            .field(
66                "cocpu_saradc1_int_ena",
67                &format_args!("{}", self.cocpu_saradc1_int_ena().bit()),
68            )
69            .field(
70                "cocpu_saradc2_int_ena",
71                &format_args!("{}", self.cocpu_saradc2_int_ena().bit()),
72            )
73            .field(
74                "cocpu_saradc1_error_int_ena",
75                &format_args!("{}", self.cocpu_saradc1_error_int_ena().bit()),
76            )
77            .field(
78                "cocpu_saradc2_error_int_ena",
79                &format_args!("{}", self.cocpu_saradc2_error_int_ena().bit()),
80            )
81            .field(
82                "cocpu_saradc1_wake_int_ena",
83                &format_args!("{}", self.cocpu_saradc1_wake_int_ena().bit()),
84            )
85            .field(
86                "cocpu_saradc2_wake_int_ena",
87                &format_args!("{}", self.cocpu_saradc2_wake_int_ena().bit()),
88            )
89            .finish()
90    }
91}
92#[cfg(feature = "impl-register-debug")]
93impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
94    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
95        core::fmt::Debug::fmt(&self.read(), f)
96    }
97}
98impl W {
99    #[doc = "Bit 0 - ADC1 Conversion is done, int enable."]
100    #[inline(always)]
101    #[must_use]
102    pub fn cocpu_saradc1_int_ena(&mut self) -> COCPU_SARADC1_INT_ENA_W<INT_ENA_SPEC> {
103        COCPU_SARADC1_INT_ENA_W::new(self, 0)
104    }
105    #[doc = "Bit 1 - ADC2 Conversion is done, int enable."]
106    #[inline(always)]
107    #[must_use]
108    pub fn cocpu_saradc2_int_ena(&mut self) -> COCPU_SARADC2_INT_ENA_W<INT_ENA_SPEC> {
109        COCPU_SARADC2_INT_ENA_W::new(self, 1)
110    }
111    #[doc = "Bit 2 - An errro occurs from ADC1, int enable."]
112    #[inline(always)]
113    #[must_use]
114    pub fn cocpu_saradc1_error_int_ena(&mut self) -> COCPU_SARADC1_ERROR_INT_ENA_W<INT_ENA_SPEC> {
115        COCPU_SARADC1_ERROR_INT_ENA_W::new(self, 2)
116    }
117    #[doc = "Bit 3 - An errro occurs from ADC2, int enable."]
118    #[inline(always)]
119    #[must_use]
120    pub fn cocpu_saradc2_error_int_ena(&mut self) -> COCPU_SARADC2_ERROR_INT_ENA_W<INT_ENA_SPEC> {
121        COCPU_SARADC2_ERROR_INT_ENA_W::new(self, 3)
122    }
123    #[doc = "Bit 4 - A wakeup event is triggered from ADC1, int enable."]
124    #[inline(always)]
125    #[must_use]
126    pub fn cocpu_saradc1_wake_int_ena(&mut self) -> COCPU_SARADC1_WAKE_INT_ENA_W<INT_ENA_SPEC> {
127        COCPU_SARADC1_WAKE_INT_ENA_W::new(self, 4)
128    }
129    #[doc = "Bit 5 - A wakeup event is triggered from ADC2, int enable."]
130    #[inline(always)]
131    #[must_use]
132    pub fn cocpu_saradc2_wake_int_ena(&mut self) -> COCPU_SARADC2_WAKE_INT_ENA_W<INT_ENA_SPEC> {
133        COCPU_SARADC2_WAKE_INT_ENA_W::new(self, 5)
134    }
135}
136#[doc = "Interrupt enable registers.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct INT_ENA_SPEC;
138impl crate::RegisterSpec for INT_ENA_SPEC {
139    type Ux = u32;
140}
141#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
142impl crate::Readable for INT_ENA_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
144impl crate::Writable for INT_ENA_SPEC {
145    type Safety = crate::Unsafe;
146    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets INT_ENA to value 0"]
150impl crate::Resettable for INT_ENA_SPEC {
151    const RESET_VALUE: u32 = 0;
152}
esp32p4/lp_adc/int_ena.rs

esp32p4/lp_adc/
int_ena.rs
