esp32p4/hp_sys_clkrst/
peri_clk_ctrl117.rs

1#[doc = "Register `PERI_CLK_CTRL117` reader"]
2pub type R = crate::R<PERI_CLK_CTRL117_SPEC>;
3#[doc = "Register `PERI_CLK_CTRL117` writer"]
4pub type W = crate::W<PERI_CLK_CTRL117_SPEC>;
5#[doc = "Field `GPSPI3_HS_CLK_DIV_NUM` reader - Reserved"]
6pub type GPSPI3_HS_CLK_DIV_NUM_R = crate::FieldReader;
7#[doc = "Field `GPSPI3_HS_CLK_DIV_NUM` writer - Reserved"]
8pub type GPSPI3_HS_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `GPSPI3_MST_CLK_DIV_NUM` reader - Reserved"]
10pub type GPSPI3_MST_CLK_DIV_NUM_R = crate::FieldReader;
11#[doc = "Field `GPSPI3_MST_CLK_DIV_NUM` writer - Reserved"]
12pub type GPSPI3_MST_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `GPSPI3_MST_CLK_EN` reader - Reserved"]
14pub type GPSPI3_MST_CLK_EN_R = crate::BitReader;
15#[doc = "Field `GPSPI3_MST_CLK_EN` writer - Reserved"]
16pub type GPSPI3_MST_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `PARLIO_RX_CLK_SRC_SEL` reader - Reserved"]
18pub type PARLIO_RX_CLK_SRC_SEL_R = crate::FieldReader;
19#[doc = "Field `PARLIO_RX_CLK_SRC_SEL` writer - Reserved"]
20pub type PARLIO_RX_CLK_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `PARLIO_RX_CLK_EN` reader - Reserved"]
22pub type PARLIO_RX_CLK_EN_R = crate::BitReader;
23#[doc = "Field `PARLIO_RX_CLK_EN` writer - Reserved"]
24pub type PARLIO_RX_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `PARLIO_RX_CLK_DIV_NUM` reader - Reserved"]
26pub type PARLIO_RX_CLK_DIV_NUM_R = crate::FieldReader;
27#[doc = "Field `PARLIO_RX_CLK_DIV_NUM` writer - Reserved"]
28pub type PARLIO_RX_CLK_DIV_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
29impl R {
30    #[doc = "Bits 0:7 - Reserved"]
31    #[inline(always)]
32    pub fn gpspi3_hs_clk_div_num(&self) -> GPSPI3_HS_CLK_DIV_NUM_R {
33        GPSPI3_HS_CLK_DIV_NUM_R::new((self.bits & 0xff) as u8)
34    }
35    #[doc = "Bits 8:15 - Reserved"]
36    #[inline(always)]
37    pub fn gpspi3_mst_clk_div_num(&self) -> GPSPI3_MST_CLK_DIV_NUM_R {
38        GPSPI3_MST_CLK_DIV_NUM_R::new(((self.bits >> 8) & 0xff) as u8)
39    }
40    #[doc = "Bit 16 - Reserved"]
41    #[inline(always)]
42    pub fn gpspi3_mst_clk_en(&self) -> GPSPI3_MST_CLK_EN_R {
43        GPSPI3_MST_CLK_EN_R::new(((self.bits >> 16) & 1) != 0)
44    }
45    #[doc = "Bits 17:18 - Reserved"]
46    #[inline(always)]
47    pub fn parlio_rx_clk_src_sel(&self) -> PARLIO_RX_CLK_SRC_SEL_R {
48        PARLIO_RX_CLK_SRC_SEL_R::new(((self.bits >> 17) & 3) as u8)
49    }
50    #[doc = "Bit 19 - Reserved"]
51    #[inline(always)]
52    pub fn parlio_rx_clk_en(&self) -> PARLIO_RX_CLK_EN_R {
53        PARLIO_RX_CLK_EN_R::new(((self.bits >> 19) & 1) != 0)
54    }
55    #[doc = "Bits 20:27 - Reserved"]
56    #[inline(always)]
57    pub fn parlio_rx_clk_div_num(&self) -> PARLIO_RX_CLK_DIV_NUM_R {
58        PARLIO_RX_CLK_DIV_NUM_R::new(((self.bits >> 20) & 0xff) as u8)
59    }
60}
61#[cfg(feature = "impl-register-debug")]
62impl core::fmt::Debug for R {
63    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
64        f.debug_struct("PERI_CLK_CTRL117")
65            .field(
66                "gpspi3_hs_clk_div_num",
67                &format_args!("{}", self.gpspi3_hs_clk_div_num().bits()),
68            )
69            .field(
70                "gpspi3_mst_clk_div_num",
71                &format_args!("{}", self.gpspi3_mst_clk_div_num().bits()),
72            )
73            .field(
74                "gpspi3_mst_clk_en",
75                &format_args!("{}", self.gpspi3_mst_clk_en().bit()),
76            )
77            .field(
78                "parlio_rx_clk_src_sel",
79                &format_args!("{}", self.parlio_rx_clk_src_sel().bits()),
80            )
81            .field(
82                "parlio_rx_clk_en",
83                &format_args!("{}", self.parlio_rx_clk_en().bit()),
84            )
85            .field(
86                "parlio_rx_clk_div_num",
87                &format_args!("{}", self.parlio_rx_clk_div_num().bits()),
88            )
89            .finish()
90    }
91}
92#[cfg(feature = "impl-register-debug")]
93impl core::fmt::Debug for crate::generic::Reg<PERI_CLK_CTRL117_SPEC> {
94    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
95        core::fmt::Debug::fmt(&self.read(), f)
96    }
97}
98impl W {
99    #[doc = "Bits 0:7 - Reserved"]
100    #[inline(always)]
101    #[must_use]
102    pub fn gpspi3_hs_clk_div_num(&mut self) -> GPSPI3_HS_CLK_DIV_NUM_W<PERI_CLK_CTRL117_SPEC> {
103        GPSPI3_HS_CLK_DIV_NUM_W::new(self, 0)
104    }
105    #[doc = "Bits 8:15 - Reserved"]
106    #[inline(always)]
107    #[must_use]
108    pub fn gpspi3_mst_clk_div_num(&mut self) -> GPSPI3_MST_CLK_DIV_NUM_W<PERI_CLK_CTRL117_SPEC> {
109        GPSPI3_MST_CLK_DIV_NUM_W::new(self, 8)
110    }
111    #[doc = "Bit 16 - Reserved"]
112    #[inline(always)]
113    #[must_use]
114    pub fn gpspi3_mst_clk_en(&mut self) -> GPSPI3_MST_CLK_EN_W<PERI_CLK_CTRL117_SPEC> {
115        GPSPI3_MST_CLK_EN_W::new(self, 16)
116    }
117    #[doc = "Bits 17:18 - Reserved"]
118    #[inline(always)]
119    #[must_use]
120    pub fn parlio_rx_clk_src_sel(&mut self) -> PARLIO_RX_CLK_SRC_SEL_W<PERI_CLK_CTRL117_SPEC> {
121        PARLIO_RX_CLK_SRC_SEL_W::new(self, 17)
122    }
123    #[doc = "Bit 19 - Reserved"]
124    #[inline(always)]
125    #[must_use]
126    pub fn parlio_rx_clk_en(&mut self) -> PARLIO_RX_CLK_EN_W<PERI_CLK_CTRL117_SPEC> {
127        PARLIO_RX_CLK_EN_W::new(self, 19)
128    }
129    #[doc = "Bits 20:27 - Reserved"]
130    #[inline(always)]
131    #[must_use]
132    pub fn parlio_rx_clk_div_num(&mut self) -> PARLIO_RX_CLK_DIV_NUM_W<PERI_CLK_CTRL117_SPEC> {
133        PARLIO_RX_CLK_DIV_NUM_W::new(self, 20)
134    }
135}
136#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`peri_clk_ctrl117::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`peri_clk_ctrl117::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
137pub struct PERI_CLK_CTRL117_SPEC;
138impl crate::RegisterSpec for PERI_CLK_CTRL117_SPEC {
139    type Ux = u32;
140}
141#[doc = "`read()` method returns [`peri_clk_ctrl117::R`](R) reader structure"]
142impl crate::Readable for PERI_CLK_CTRL117_SPEC {}
143#[doc = "`write(|w| ..)` method takes [`peri_clk_ctrl117::W`](W) writer structure"]
144impl crate::Writable for PERI_CLK_CTRL117_SPEC {
145    type Safety = crate::Unsafe;
146    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
147    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
148}
149#[doc = "`reset()` method sets PERI_CLK_CTRL117 to value 0x0001_0000"]
150impl crate::Resettable for PERI_CLK_CTRL117_SPEC {
151    const RESET_VALUE: u32 = 0x0001_0000;
152}
esp32p4/hp_sys_clkrst/peri_clk_ctrl117.rs

esp32p4/hp_sys_clkrst/
peri_clk_ctrl117.rs
