esp32p4/hp_sys/
cpu_waiti_conf.rs

1#[doc = "Register `CPU_WAITI_CONF` reader"]
2pub type R = crate::R<CPU_WAITI_CONF_SPEC>;
3#[doc = "Register `CPU_WAITI_CONF` writer"]
4pub type W = crate::W<CPU_WAITI_CONF_SPEC>;
5#[doc = "Field `CPU_WAIT_MODE_FORCE_ON` reader - Set 1 to force cpu_waiti_clk enable."]
6pub type CPU_WAIT_MODE_FORCE_ON_R = crate::BitReader;
7#[doc = "Field `CPU_WAIT_MODE_FORCE_ON` writer - Set 1 to force cpu_waiti_clk enable."]
8pub type CPU_WAIT_MODE_FORCE_ON_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CPU_WAITI_DELAY_NUM` reader - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
10pub type CPU_WAITI_DELAY_NUM_R = crate::FieldReader;
11#[doc = "Field `CPU_WAITI_DELAY_NUM` writer - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
12pub type CPU_WAITI_DELAY_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13impl R {
14    #[doc = "Bit 0 - Set 1 to force cpu_waiti_clk enable."]
15    #[inline(always)]
16    pub fn cpu_wait_mode_force_on(&self) -> CPU_WAIT_MODE_FORCE_ON_R {
17        CPU_WAIT_MODE_FORCE_ON_R::new((self.bits & 1) != 0)
18    }
19    #[doc = "Bits 1:4 - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
20    #[inline(always)]
21    pub fn cpu_waiti_delay_num(&self) -> CPU_WAITI_DELAY_NUM_R {
22        CPU_WAITI_DELAY_NUM_R::new(((self.bits >> 1) & 0x0f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("CPU_WAITI_CONF")
29            .field(
30                "cpu_wait_mode_force_on",
31                &format_args!("{}", self.cpu_wait_mode_force_on().bit()),
32            )
33            .field(
34                "cpu_waiti_delay_num",
35                &format_args!("{}", self.cpu_waiti_delay_num().bits()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<CPU_WAITI_CONF_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bit 0 - Set 1 to force cpu_waiti_clk enable."]
48    #[inline(always)]
49    #[must_use]
50    pub fn cpu_wait_mode_force_on(&mut self) -> CPU_WAIT_MODE_FORCE_ON_W<CPU_WAITI_CONF_SPEC> {
51        CPU_WAIT_MODE_FORCE_ON_W::new(self, 0)
52    }
53    #[doc = "Bits 1:4 - This field used to set delay cycle when cpu enter waiti mode, after delay waiti_clk will close"]
54    #[inline(always)]
55    #[must_use]
56    pub fn cpu_waiti_delay_num(&mut self) -> CPU_WAITI_DELAY_NUM_W<CPU_WAITI_CONF_SPEC> {
57        CPU_WAITI_DELAY_NUM_W::new(self, 1)
58    }
59}
60#[doc = "CPU_WAITI configuration register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cpu_waiti_conf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cpu_waiti_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct CPU_WAITI_CONF_SPEC;
62impl crate::RegisterSpec for CPU_WAITI_CONF_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`cpu_waiti_conf::R`](R) reader structure"]
66impl crate::Readable for CPU_WAITI_CONF_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`cpu_waiti_conf::W`](W) writer structure"]
68impl crate::Writable for CPU_WAITI_CONF_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets CPU_WAITI_CONF to value 0x01"]
74impl crate::Resettable for CPU_WAITI_CONF_SPEC {
75    const RESET_VALUE: u32 = 0x01;
76}
esp32p4/hp_sys/cpu_waiti_conf.rs

esp32p4/hp_sys/
cpu_waiti_conf.rs
