esp32p4/dma/ch/
intstatus_enable0.rs

1#[doc = "Register `INTSTATUS_ENABLE0` reader"]
2pub type R = crate::R<INTSTATUS_ENABLE0_SPEC>;
3#[doc = "Register `INTSTATUS_ENABLE0` writer"]
4pub type W = crate::W<INTSTATUS_ENABLE0_SPEC>;
5#[doc = "Field `CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT` reader - NA"]
6pub type CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_R = crate::BitReader;
7#[doc = "Field `CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT` writer - NA"]
8pub type CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CH1_ENABLE_DMA_TFR_DONE_INTSTAT` reader - NA"]
10pub type CH1_ENABLE_DMA_TFR_DONE_INTSTAT_R = crate::BitReader;
11#[doc = "Field `CH1_ENABLE_DMA_TFR_DONE_INTSTAT` writer - NA"]
12pub type CH1_ENABLE_DMA_TFR_DONE_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CH1_ENABLE_SRC_TRANSCOMP_INTSTAT` reader - NA"]
14pub type CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_R = crate::BitReader;
15#[doc = "Field `CH1_ENABLE_SRC_TRANSCOMP_INTSTAT` writer - NA"]
16pub type CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CH1_ENABLE_DST_TRANSCOMP_INTSTAT` reader - NA"]
18pub type CH1_ENABLE_DST_TRANSCOMP_INTSTAT_R = crate::BitReader;
19#[doc = "Field `CH1_ENABLE_DST_TRANSCOMP_INTSTAT` writer - NA"]
20pub type CH1_ENABLE_DST_TRANSCOMP_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `CH1_ENABLE_SRC_DEC_ERR_INTSTAT` reader - NA"]
22pub type CH1_ENABLE_SRC_DEC_ERR_INTSTAT_R = crate::BitReader;
23#[doc = "Field `CH1_ENABLE_SRC_DEC_ERR_INTSTAT` writer - NA"]
24pub type CH1_ENABLE_SRC_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `CH1_ENABLE_DST_DEC_ERR_INTSTAT` reader - NA"]
26pub type CH1_ENABLE_DST_DEC_ERR_INTSTAT_R = crate::BitReader;
27#[doc = "Field `CH1_ENABLE_DST_DEC_ERR_INTSTAT` writer - NA"]
28pub type CH1_ENABLE_DST_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CH1_ENABLE_SRC_SLV_ERR_INTSTAT` reader - NA"]
30pub type CH1_ENABLE_SRC_SLV_ERR_INTSTAT_R = crate::BitReader;
31#[doc = "Field `CH1_ENABLE_SRC_SLV_ERR_INTSTAT` writer - NA"]
32pub type CH1_ENABLE_SRC_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `CH1_ENABLE_DST_SLV_ERR_INTSTAT` reader - NA"]
34pub type CH1_ENABLE_DST_SLV_ERR_INTSTAT_R = crate::BitReader;
35#[doc = "Field `CH1_ENABLE_DST_SLV_ERR_INTSTAT` writer - NA"]
36pub type CH1_ENABLE_DST_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT` reader - NA"]
38pub type CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R = crate::BitReader;
39#[doc = "Field `CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT` writer - NA"]
40pub type CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT` reader - NA"]
42pub type CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R = crate::BitReader;
43#[doc = "Field `CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT` writer - NA"]
44pub type CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT` reader - NA"]
46pub type CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R = crate::BitReader;
47#[doc = "Field `CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT` writer - NA"]
48pub type CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT` reader - NA"]
50pub type CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R = crate::BitReader;
51#[doc = "Field `CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT` writer - NA"]
52pub type CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` reader - NA"]
54pub type CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R = crate::BitReader;
55#[doc = "Field `CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT` writer - NA"]
56pub type CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` reader - NA"]
58pub type CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R = crate::BitReader;
59#[doc = "Field `CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT` writer - NA"]
60pub type CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT` reader - NA"]
62pub type CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_R = crate::BitReader;
63#[doc = "Field `CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT` writer - NA"]
64pub type CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` reader - NA"]
66pub type CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R = crate::BitReader;
67#[doc = "Field `CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT` writer - NA"]
68pub type CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` reader - NA"]
70pub type CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R = crate::BitReader;
71#[doc = "Field `CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT` writer - NA"]
72pub type CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` reader - NA"]
74pub type CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R = crate::BitReader;
75#[doc = "Field `CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT` writer - NA"]
76pub type CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` reader - NA"]
78pub type CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R = crate::BitReader;
79#[doc = "Field `CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT` writer - NA"]
80pub type CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` reader - NA"]
82pub type CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R = crate::BitReader;
83#[doc = "Field `CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT` writer - NA"]
84pub type CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT` reader - NA"]
86pub type CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R = crate::BitReader;
87#[doc = "Field `CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT` reader - NA"]
88pub type CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_R = crate::BitReader;
89#[doc = "Field `CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT` writer - NA"]
90pub type CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
91#[doc = "Field `CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT` reader - NA"]
92pub type CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R = crate::BitReader;
93#[doc = "Field `CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT` writer - NA"]
94pub type CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
95#[doc = "Field `CH1_ENABLE_CH_SUSPENDED_INTSTAT` reader - NA"]
96pub type CH1_ENABLE_CH_SUSPENDED_INTSTAT_R = crate::BitReader;
97#[doc = "Field `CH1_ENABLE_CH_SUSPENDED_INTSTAT` writer - NA"]
98pub type CH1_ENABLE_CH_SUSPENDED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
99#[doc = "Field `CH1_ENABLE_CH_DISABLED_INTSTAT` reader - NA"]
100pub type CH1_ENABLE_CH_DISABLED_INTSTAT_R = crate::BitReader;
101#[doc = "Field `CH1_ENABLE_CH_DISABLED_INTSTAT` writer - NA"]
102pub type CH1_ENABLE_CH_DISABLED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
103#[doc = "Field `CH1_ENABLE_CH_ABORTED_INTSTAT` reader - NA"]
104pub type CH1_ENABLE_CH_ABORTED_INTSTAT_R = crate::BitReader;
105#[doc = "Field `CH1_ENABLE_CH_ABORTED_INTSTAT` writer - NA"]
106pub type CH1_ENABLE_CH_ABORTED_INTSTAT_W<'a, REG> = crate::BitWriter<'a, REG>;
107impl R {
108    #[doc = "Bit 0 - NA"]
109    #[inline(always)]
110    pub fn ch1_enable_block_tfr_done_intstat(&self) -> CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_R {
111        CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_R::new((self.bits & 1) != 0)
112    }
113    #[doc = "Bit 1 - NA"]
114    #[inline(always)]
115    pub fn ch1_enable_dma_tfr_done_intstat(&self) -> CH1_ENABLE_DMA_TFR_DONE_INTSTAT_R {
116        CH1_ENABLE_DMA_TFR_DONE_INTSTAT_R::new(((self.bits >> 1) & 1) != 0)
117    }
118    #[doc = "Bit 3 - NA"]
119    #[inline(always)]
120    pub fn ch1_enable_src_transcomp_intstat(&self) -> CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_R {
121        CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_R::new(((self.bits >> 3) & 1) != 0)
122    }
123    #[doc = "Bit 4 - NA"]
124    #[inline(always)]
125    pub fn ch1_enable_dst_transcomp_intstat(&self) -> CH1_ENABLE_DST_TRANSCOMP_INTSTAT_R {
126        CH1_ENABLE_DST_TRANSCOMP_INTSTAT_R::new(((self.bits >> 4) & 1) != 0)
127    }
128    #[doc = "Bit 5 - NA"]
129    #[inline(always)]
130    pub fn ch1_enable_src_dec_err_intstat(&self) -> CH1_ENABLE_SRC_DEC_ERR_INTSTAT_R {
131        CH1_ENABLE_SRC_DEC_ERR_INTSTAT_R::new(((self.bits >> 5) & 1) != 0)
132    }
133    #[doc = "Bit 6 - NA"]
134    #[inline(always)]
135    pub fn ch1_enable_dst_dec_err_intstat(&self) -> CH1_ENABLE_DST_DEC_ERR_INTSTAT_R {
136        CH1_ENABLE_DST_DEC_ERR_INTSTAT_R::new(((self.bits >> 6) & 1) != 0)
137    }
138    #[doc = "Bit 7 - NA"]
139    #[inline(always)]
140    pub fn ch1_enable_src_slv_err_intstat(&self) -> CH1_ENABLE_SRC_SLV_ERR_INTSTAT_R {
141        CH1_ENABLE_SRC_SLV_ERR_INTSTAT_R::new(((self.bits >> 7) & 1) != 0)
142    }
143    #[doc = "Bit 8 - NA"]
144    #[inline(always)]
145    pub fn ch1_enable_dst_slv_err_intstat(&self) -> CH1_ENABLE_DST_SLV_ERR_INTSTAT_R {
146        CH1_ENABLE_DST_SLV_ERR_INTSTAT_R::new(((self.bits >> 8) & 1) != 0)
147    }
148    #[doc = "Bit 9 - NA"]
149    #[inline(always)]
150    pub fn ch1_enable_lli_rd_dec_err_intstat(&self) -> CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R {
151        CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_R::new(((self.bits >> 9) & 1) != 0)
152    }
153    #[doc = "Bit 10 - NA"]
154    #[inline(always)]
155    pub fn ch1_enable_lli_wr_dec_err_intstat(&self) -> CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R {
156        CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_R::new(((self.bits >> 10) & 1) != 0)
157    }
158    #[doc = "Bit 11 - NA"]
159    #[inline(always)]
160    pub fn ch1_enable_lli_rd_slv_err_intstat(&self) -> CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R {
161        CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_R::new(((self.bits >> 11) & 1) != 0)
162    }
163    #[doc = "Bit 12 - NA"]
164    #[inline(always)]
165    pub fn ch1_enable_lli_wr_slv_err_intstat(&self) -> CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R {
166        CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_R::new(((self.bits >> 12) & 1) != 0)
167    }
168    #[doc = "Bit 13 - NA"]
169    #[inline(always)]
170    pub fn ch1_enable_shadowreg_or_lli_invalid_err_intstat(
171        &self,
172    ) -> CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R {
173        CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_R::new(((self.bits >> 13) & 1) != 0)
174    }
175    #[doc = "Bit 14 - NA"]
176    #[inline(always)]
177    pub fn ch1_enable_slvif_multiblktype_err_intstat(
178        &self,
179    ) -> CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R {
180        CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_R::new(((self.bits >> 14) & 1) != 0)
181    }
182    #[doc = "Bit 16 - NA"]
183    #[inline(always)]
184    pub fn ch1_enable_slvif_dec_err_intstat(&self) -> CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_R {
185        CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_R::new(((self.bits >> 16) & 1) != 0)
186    }
187    #[doc = "Bit 17 - NA"]
188    #[inline(always)]
189    pub fn ch1_enable_slvif_wr2ro_err_intstat(&self) -> CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R {
190        CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_R::new(((self.bits >> 17) & 1) != 0)
191    }
192    #[doc = "Bit 18 - NA"]
193    #[inline(always)]
194    pub fn ch1_enable_slvif_rd2rwo_err_intstat(&self) -> CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R {
195        CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_R::new(((self.bits >> 18) & 1) != 0)
196    }
197    #[doc = "Bit 19 - NA"]
198    #[inline(always)]
199    pub fn ch1_enable_slvif_wronchen_err_intstat(&self) -> CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R {
200        CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_R::new(((self.bits >> 19) & 1) != 0)
201    }
202    #[doc = "Bit 20 - NA"]
203    #[inline(always)]
204    pub fn ch1_enable_slvif_shadowreg_wron_valid_err_intstat(
205        &self,
206    ) -> CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R {
207        CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_R::new(((self.bits >> 20) & 1) != 0)
208    }
209    #[doc = "Bit 21 - NA"]
210    #[inline(always)]
211    pub fn ch1_enable_slvif_wronhold_err_intstat(&self) -> CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R {
212        CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_R::new(((self.bits >> 21) & 1) != 0)
213    }
214    #[doc = "Bit 25 - NA"]
215    #[inline(always)]
216    pub fn ch1_enable_slvif_wrparity_err_intstat(&self) -> CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R {
217        CH1_ENABLE_SLVIF_WRPARITY_ERR_INTSTAT_R::new(((self.bits >> 25) & 1) != 0)
218    }
219    #[doc = "Bit 27 - NA"]
220    #[inline(always)]
221    pub fn ch1_enable_ch_lock_cleared_intstat(&self) -> CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_R {
222        CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_R::new(((self.bits >> 27) & 1) != 0)
223    }
224    #[doc = "Bit 28 - NA"]
225    #[inline(always)]
226    pub fn ch1_enable_ch_src_suspended_intstat(&self) -> CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R {
227        CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_R::new(((self.bits >> 28) & 1) != 0)
228    }
229    #[doc = "Bit 29 - NA"]
230    #[inline(always)]
231    pub fn ch1_enable_ch_suspended_intstat(&self) -> CH1_ENABLE_CH_SUSPENDED_INTSTAT_R {
232        CH1_ENABLE_CH_SUSPENDED_INTSTAT_R::new(((self.bits >> 29) & 1) != 0)
233    }
234    #[doc = "Bit 30 - NA"]
235    #[inline(always)]
236    pub fn ch1_enable_ch_disabled_intstat(&self) -> CH1_ENABLE_CH_DISABLED_INTSTAT_R {
237        CH1_ENABLE_CH_DISABLED_INTSTAT_R::new(((self.bits >> 30) & 1) != 0)
238    }
239    #[doc = "Bit 31 - NA"]
240    #[inline(always)]
241    pub fn ch1_enable_ch_aborted_intstat(&self) -> CH1_ENABLE_CH_ABORTED_INTSTAT_R {
242        CH1_ENABLE_CH_ABORTED_INTSTAT_R::new(((self.bits >> 31) & 1) != 0)
243    }
244}
245#[cfg(feature = "impl-register-debug")]
246impl core::fmt::Debug for R {
247    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
248        f.debug_struct("INTSTATUS_ENABLE0")
249            .field(
250                "ch1_enable_block_tfr_done_intstat",
251                &format_args!("{}", self.ch1_enable_block_tfr_done_intstat().bit()),
252            )
253            .field(
254                "ch1_enable_dma_tfr_done_intstat",
255                &format_args!("{}", self.ch1_enable_dma_tfr_done_intstat().bit()),
256            )
257            .field(
258                "ch1_enable_src_transcomp_intstat",
259                &format_args!("{}", self.ch1_enable_src_transcomp_intstat().bit()),
260            )
261            .field(
262                "ch1_enable_dst_transcomp_intstat",
263                &format_args!("{}", self.ch1_enable_dst_transcomp_intstat().bit()),
264            )
265            .field(
266                "ch1_enable_src_dec_err_intstat",
267                &format_args!("{}", self.ch1_enable_src_dec_err_intstat().bit()),
268            )
269            .field(
270                "ch1_enable_dst_dec_err_intstat",
271                &format_args!("{}", self.ch1_enable_dst_dec_err_intstat().bit()),
272            )
273            .field(
274                "ch1_enable_src_slv_err_intstat",
275                &format_args!("{}", self.ch1_enable_src_slv_err_intstat().bit()),
276            )
277            .field(
278                "ch1_enable_dst_slv_err_intstat",
279                &format_args!("{}", self.ch1_enable_dst_slv_err_intstat().bit()),
280            )
281            .field(
282                "ch1_enable_lli_rd_dec_err_intstat",
283                &format_args!("{}", self.ch1_enable_lli_rd_dec_err_intstat().bit()),
284            )
285            .field(
286                "ch1_enable_lli_wr_dec_err_intstat",
287                &format_args!("{}", self.ch1_enable_lli_wr_dec_err_intstat().bit()),
288            )
289            .field(
290                "ch1_enable_lli_rd_slv_err_intstat",
291                &format_args!("{}", self.ch1_enable_lli_rd_slv_err_intstat().bit()),
292            )
293            .field(
294                "ch1_enable_lli_wr_slv_err_intstat",
295                &format_args!("{}", self.ch1_enable_lli_wr_slv_err_intstat().bit()),
296            )
297            .field(
298                "ch1_enable_shadowreg_or_lli_invalid_err_intstat",
299                &format_args!(
300                    "{}",
301                    self.ch1_enable_shadowreg_or_lli_invalid_err_intstat().bit()
302                ),
303            )
304            .field(
305                "ch1_enable_slvif_multiblktype_err_intstat",
306                &format_args!("{}", self.ch1_enable_slvif_multiblktype_err_intstat().bit()),
307            )
308            .field(
309                "ch1_enable_slvif_dec_err_intstat",
310                &format_args!("{}", self.ch1_enable_slvif_dec_err_intstat().bit()),
311            )
312            .field(
313                "ch1_enable_slvif_wr2ro_err_intstat",
314                &format_args!("{}", self.ch1_enable_slvif_wr2ro_err_intstat().bit()),
315            )
316            .field(
317                "ch1_enable_slvif_rd2rwo_err_intstat",
318                &format_args!("{}", self.ch1_enable_slvif_rd2rwo_err_intstat().bit()),
319            )
320            .field(
321                "ch1_enable_slvif_wronchen_err_intstat",
322                &format_args!("{}", self.ch1_enable_slvif_wronchen_err_intstat().bit()),
323            )
324            .field(
325                "ch1_enable_slvif_shadowreg_wron_valid_err_intstat",
326                &format_args!(
327                    "{}",
328                    self.ch1_enable_slvif_shadowreg_wron_valid_err_intstat()
329                        .bit()
330                ),
331            )
332            .field(
333                "ch1_enable_slvif_wronhold_err_intstat",
334                &format_args!("{}", self.ch1_enable_slvif_wronhold_err_intstat().bit()),
335            )
336            .field(
337                "ch1_enable_slvif_wrparity_err_intstat",
338                &format_args!("{}", self.ch1_enable_slvif_wrparity_err_intstat().bit()),
339            )
340            .field(
341                "ch1_enable_ch_lock_cleared_intstat",
342                &format_args!("{}", self.ch1_enable_ch_lock_cleared_intstat().bit()),
343            )
344            .field(
345                "ch1_enable_ch_src_suspended_intstat",
346                &format_args!("{}", self.ch1_enable_ch_src_suspended_intstat().bit()),
347            )
348            .field(
349                "ch1_enable_ch_suspended_intstat",
350                &format_args!("{}", self.ch1_enable_ch_suspended_intstat().bit()),
351            )
352            .field(
353                "ch1_enable_ch_disabled_intstat",
354                &format_args!("{}", self.ch1_enable_ch_disabled_intstat().bit()),
355            )
356            .field(
357                "ch1_enable_ch_aborted_intstat",
358                &format_args!("{}", self.ch1_enable_ch_aborted_intstat().bit()),
359            )
360            .finish()
361    }
362}
363#[cfg(feature = "impl-register-debug")]
364impl core::fmt::Debug for crate::generic::Reg<INTSTATUS_ENABLE0_SPEC> {
365    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
366        core::fmt::Debug::fmt(&self.read(), f)
367    }
368}
369impl W {
370    #[doc = "Bit 0 - NA"]
371    #[inline(always)]
372    #[must_use]
373    pub fn ch1_enable_block_tfr_done_intstat(
374        &mut self,
375    ) -> CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
376        CH1_ENABLE_BLOCK_TFR_DONE_INTSTAT_W::new(self, 0)
377    }
378    #[doc = "Bit 1 - NA"]
379    #[inline(always)]
380    #[must_use]
381    pub fn ch1_enable_dma_tfr_done_intstat(
382        &mut self,
383    ) -> CH1_ENABLE_DMA_TFR_DONE_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
384        CH1_ENABLE_DMA_TFR_DONE_INTSTAT_W::new(self, 1)
385    }
386    #[doc = "Bit 3 - NA"]
387    #[inline(always)]
388    #[must_use]
389    pub fn ch1_enable_src_transcomp_intstat(
390        &mut self,
391    ) -> CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
392        CH1_ENABLE_SRC_TRANSCOMP_INTSTAT_W::new(self, 3)
393    }
394    #[doc = "Bit 4 - NA"]
395    #[inline(always)]
396    #[must_use]
397    pub fn ch1_enable_dst_transcomp_intstat(
398        &mut self,
399    ) -> CH1_ENABLE_DST_TRANSCOMP_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
400        CH1_ENABLE_DST_TRANSCOMP_INTSTAT_W::new(self, 4)
401    }
402    #[doc = "Bit 5 - NA"]
403    #[inline(always)]
404    #[must_use]
405    pub fn ch1_enable_src_dec_err_intstat(
406        &mut self,
407    ) -> CH1_ENABLE_SRC_DEC_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
408        CH1_ENABLE_SRC_DEC_ERR_INTSTAT_W::new(self, 5)
409    }
410    #[doc = "Bit 6 - NA"]
411    #[inline(always)]
412    #[must_use]
413    pub fn ch1_enable_dst_dec_err_intstat(
414        &mut self,
415    ) -> CH1_ENABLE_DST_DEC_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
416        CH1_ENABLE_DST_DEC_ERR_INTSTAT_W::new(self, 6)
417    }
418    #[doc = "Bit 7 - NA"]
419    #[inline(always)]
420    #[must_use]
421    pub fn ch1_enable_src_slv_err_intstat(
422        &mut self,
423    ) -> CH1_ENABLE_SRC_SLV_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
424        CH1_ENABLE_SRC_SLV_ERR_INTSTAT_W::new(self, 7)
425    }
426    #[doc = "Bit 8 - NA"]
427    #[inline(always)]
428    #[must_use]
429    pub fn ch1_enable_dst_slv_err_intstat(
430        &mut self,
431    ) -> CH1_ENABLE_DST_SLV_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
432        CH1_ENABLE_DST_SLV_ERR_INTSTAT_W::new(self, 8)
433    }
434    #[doc = "Bit 9 - NA"]
435    #[inline(always)]
436    #[must_use]
437    pub fn ch1_enable_lli_rd_dec_err_intstat(
438        &mut self,
439    ) -> CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
440        CH1_ENABLE_LLI_RD_DEC_ERR_INTSTAT_W::new(self, 9)
441    }
442    #[doc = "Bit 10 - NA"]
443    #[inline(always)]
444    #[must_use]
445    pub fn ch1_enable_lli_wr_dec_err_intstat(
446        &mut self,
447    ) -> CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
448        CH1_ENABLE_LLI_WR_DEC_ERR_INTSTAT_W::new(self, 10)
449    }
450    #[doc = "Bit 11 - NA"]
451    #[inline(always)]
452    #[must_use]
453    pub fn ch1_enable_lli_rd_slv_err_intstat(
454        &mut self,
455    ) -> CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
456        CH1_ENABLE_LLI_RD_SLV_ERR_INTSTAT_W::new(self, 11)
457    }
458    #[doc = "Bit 12 - NA"]
459    #[inline(always)]
460    #[must_use]
461    pub fn ch1_enable_lli_wr_slv_err_intstat(
462        &mut self,
463    ) -> CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
464        CH1_ENABLE_LLI_WR_SLV_ERR_INTSTAT_W::new(self, 12)
465    }
466    #[doc = "Bit 13 - NA"]
467    #[inline(always)]
468    #[must_use]
469    pub fn ch1_enable_shadowreg_or_lli_invalid_err_intstat(
470        &mut self,
471    ) -> CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
472        CH1_ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT_W::new(self, 13)
473    }
474    #[doc = "Bit 14 - NA"]
475    #[inline(always)]
476    #[must_use]
477    pub fn ch1_enable_slvif_multiblktype_err_intstat(
478        &mut self,
479    ) -> CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
480        CH1_ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT_W::new(self, 14)
481    }
482    #[doc = "Bit 16 - NA"]
483    #[inline(always)]
484    #[must_use]
485    pub fn ch1_enable_slvif_dec_err_intstat(
486        &mut self,
487    ) -> CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
488        CH1_ENABLE_SLVIF_DEC_ERR_INTSTAT_W::new(self, 16)
489    }
490    #[doc = "Bit 17 - NA"]
491    #[inline(always)]
492    #[must_use]
493    pub fn ch1_enable_slvif_wr2ro_err_intstat(
494        &mut self,
495    ) -> CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
496        CH1_ENABLE_SLVIF_WR2RO_ERR_INTSTAT_W::new(self, 17)
497    }
498    #[doc = "Bit 18 - NA"]
499    #[inline(always)]
500    #[must_use]
501    pub fn ch1_enable_slvif_rd2rwo_err_intstat(
502        &mut self,
503    ) -> CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
504        CH1_ENABLE_SLVIF_RD2RWO_ERR_INTSTAT_W::new(self, 18)
505    }
506    #[doc = "Bit 19 - NA"]
507    #[inline(always)]
508    #[must_use]
509    pub fn ch1_enable_slvif_wronchen_err_intstat(
510        &mut self,
511    ) -> CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
512        CH1_ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT_W::new(self, 19)
513    }
514    #[doc = "Bit 20 - NA"]
515    #[inline(always)]
516    #[must_use]
517    pub fn ch1_enable_slvif_shadowreg_wron_valid_err_intstat(
518        &mut self,
519    ) -> CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
520        CH1_ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT_W::new(self, 20)
521    }
522    #[doc = "Bit 21 - NA"]
523    #[inline(always)]
524    #[must_use]
525    pub fn ch1_enable_slvif_wronhold_err_intstat(
526        &mut self,
527    ) -> CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
528        CH1_ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT_W::new(self, 21)
529    }
530    #[doc = "Bit 27 - NA"]
531    #[inline(always)]
532    #[must_use]
533    pub fn ch1_enable_ch_lock_cleared_intstat(
534        &mut self,
535    ) -> CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
536        CH1_ENABLE_CH_LOCK_CLEARED_INTSTAT_W::new(self, 27)
537    }
538    #[doc = "Bit 28 - NA"]
539    #[inline(always)]
540    #[must_use]
541    pub fn ch1_enable_ch_src_suspended_intstat(
542        &mut self,
543    ) -> CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
544        CH1_ENABLE_CH_SRC_SUSPENDED_INTSTAT_W::new(self, 28)
545    }
546    #[doc = "Bit 29 - NA"]
547    #[inline(always)]
548    #[must_use]
549    pub fn ch1_enable_ch_suspended_intstat(
550        &mut self,
551    ) -> CH1_ENABLE_CH_SUSPENDED_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
552        CH1_ENABLE_CH_SUSPENDED_INTSTAT_W::new(self, 29)
553    }
554    #[doc = "Bit 30 - NA"]
555    #[inline(always)]
556    #[must_use]
557    pub fn ch1_enable_ch_disabled_intstat(
558        &mut self,
559    ) -> CH1_ENABLE_CH_DISABLED_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
560        CH1_ENABLE_CH_DISABLED_INTSTAT_W::new(self, 30)
561    }
562    #[doc = "Bit 31 - NA"]
563    #[inline(always)]
564    #[must_use]
565    pub fn ch1_enable_ch_aborted_intstat(
566        &mut self,
567    ) -> CH1_ENABLE_CH_ABORTED_INTSTAT_W<INTSTATUS_ENABLE0_SPEC> {
568        CH1_ENABLE_CH_ABORTED_INTSTAT_W::new(self, 31)
569    }
570}
571#[doc = "NA\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`intstatus_enable0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intstatus_enable0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
572pub struct INTSTATUS_ENABLE0_SPEC;
573impl crate::RegisterSpec for INTSTATUS_ENABLE0_SPEC {
574    type Ux = u32;
575}
576#[doc = "`read()` method returns [`intstatus_enable0::R`](R) reader structure"]
577impl crate::Readable for INTSTATUS_ENABLE0_SPEC {}
578#[doc = "`write(|w| ..)` method takes [`intstatus_enable0::W`](W) writer structure"]
579impl crate::Writable for INTSTATUS_ENABLE0_SPEC {
580    type Safety = crate::Unsafe;
581    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
582    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
583}
584#[doc = "`reset()` method sets INTSTATUS_ENABLE0 to value 0xfa3f_7ffb"]
585impl crate::Resettable for INTSTATUS_ENABLE0_SPEC {
586    const RESET_VALUE: u32 = 0xfa3f_7ffb;
587}
esp32p4/dma/ch/intstatus_enable0.rs

esp32p4/dma/ch/
intstatus_enable0.rs
