esp32p4/axi_dma/out_ch/out_int/
clr.rs

1#[doc = "Register `CLR` writer"]
2pub type W = crate::W<CLR_SPEC>;
3#[doc = "Field `OUT_DONE` writer - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
4pub type OUT_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `OUT_EOF` writer - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
6pub type OUT_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `OUT_DSCR_ERR` writer - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
8pub type OUT_DSCR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `OUT_TOTAL_EOF` writer - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
10pub type OUT_TOTAL_EOF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `OUTFIFO_L1_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
12pub type OUTFIFO_L1_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `OUTFIFO_L1_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
14pub type OUTFIFO_L1_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `OUTFIFO_L2_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."]
16pub type OUTFIFO_L2_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `OUTFIFO_L2_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."]
18pub type OUTFIFO_L2_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `OUTFIFO_L3_OVF` writer - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."]
20pub type OUTFIFO_L3_OVF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `OUTFIFO_L3_UDF` writer - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."]
22pub type OUTFIFO_L3_UDF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[cfg(feature = "impl-register-debug")]
24impl core::fmt::Debug for crate::generic::Reg<CLR_SPEC> {
25    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
26        write!(f, "(not readable)")
27    }
28}
29impl W {
30    #[doc = "Bit 0 - Set this bit to clear the OUT_DONE_CH_INT interrupt."]
31    #[inline(always)]
32    #[must_use]
33    pub fn out_done(&mut self) -> OUT_DONE_W<CLR_SPEC> {
34        OUT_DONE_W::new(self, 0)
35    }
36    #[doc = "Bit 1 - Set this bit to clear the OUT_EOF_CH_INT interrupt."]
37    #[inline(always)]
38    #[must_use]
39    pub fn out_eof(&mut self) -> OUT_EOF_W<CLR_SPEC> {
40        OUT_EOF_W::new(self, 1)
41    }
42    #[doc = "Bit 2 - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt."]
43    #[inline(always)]
44    #[must_use]
45    pub fn out_dscr_err(&mut self) -> OUT_DSCR_ERR_W<CLR_SPEC> {
46        OUT_DSCR_ERR_W::new(self, 2)
47    }
48    #[doc = "Bit 3 - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt."]
49    #[inline(always)]
50    #[must_use]
51    pub fn out_total_eof(&mut self) -> OUT_TOTAL_EOF_W<CLR_SPEC> {
52        OUT_TOTAL_EOF_W::new(self, 3)
53    }
54    #[doc = "Bit 4 - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt."]
55    #[inline(always)]
56    #[must_use]
57    pub fn outfifo_l1_ovf(&mut self) -> OUTFIFO_L1_OVF_W<CLR_SPEC> {
58        OUTFIFO_L1_OVF_W::new(self, 4)
59    }
60    #[doc = "Bit 5 - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt."]
61    #[inline(always)]
62    #[must_use]
63    pub fn outfifo_l1_udf(&mut self) -> OUTFIFO_L1_UDF_W<CLR_SPEC> {
64        OUTFIFO_L1_UDF_W::new(self, 5)
65    }
66    #[doc = "Bit 6 - Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt."]
67    #[inline(always)]
68    #[must_use]
69    pub fn outfifo_l2_ovf(&mut self) -> OUTFIFO_L2_OVF_W<CLR_SPEC> {
70        OUTFIFO_L2_OVF_W::new(self, 6)
71    }
72    #[doc = "Bit 7 - Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt."]
73    #[inline(always)]
74    #[must_use]
75    pub fn outfifo_l2_udf(&mut self) -> OUTFIFO_L2_UDF_W<CLR_SPEC> {
76        OUTFIFO_L2_UDF_W::new(self, 7)
77    }
78    #[doc = "Bit 8 - Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt."]
79    #[inline(always)]
80    #[must_use]
81    pub fn outfifo_l3_ovf(&mut self) -> OUTFIFO_L3_OVF_W<CLR_SPEC> {
82        OUTFIFO_L3_OVF_W::new(self, 8)
83    }
84    #[doc = "Bit 9 - Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt."]
85    #[inline(always)]
86    #[must_use]
87    pub fn outfifo_l3_udf(&mut self) -> OUTFIFO_L3_UDF_W<CLR_SPEC> {
88        OUTFIFO_L3_UDF_W::new(self, 9)
89    }
90}
91#[doc = "Interrupt clear bits of channel0\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
92pub struct CLR_SPEC;
93impl crate::RegisterSpec for CLR_SPEC {
94    type Ux = u32;
95}
96#[doc = "`write(|w| ..)` method takes [`clr::W`](W) writer structure"]
97impl crate::Writable for CLR_SPEC {
98    type Safety = crate::Unsafe;
99    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
100    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x03ff;
101}
102#[doc = "`reset()` method sets CLR to value 0"]
103impl crate::Resettable for CLR_SPEC {
104    const RESET_VALUE: u32 = 0;
105}
esp32p4/axi_dma/out_ch/out_int/clr.rs

esp32p4/axi_dma/out_ch/out_int/
clr.rs
