esp32p4/axi_dma/
misc_conf.rs

1#[doc = "Register `MISC_CONF` reader"]
2pub type R = crate::R<MISC_CONF_SPEC>;
3#[doc = "Register `MISC_CONF` writer"]
4pub type W = crate::W<MISC_CONF_SPEC>;
5#[doc = "Field `AXIM_RST_WR_INTER` reader - Set this bit then clear this bit to reset the internal axi_wr FSM."]
6pub type AXIM_RST_WR_INTER_R = crate::BitReader;
7#[doc = "Field `AXIM_RST_WR_INTER` writer - Set this bit then clear this bit to reset the internal axi_wr FSM."]
8pub type AXIM_RST_WR_INTER_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `AXIM_RST_RD_INTER` reader - Set this bit then clear this bit to reset the internal axi_rd FSM."]
10pub type AXIM_RST_RD_INTER_R = crate::BitReader;
11#[doc = "Field `AXIM_RST_RD_INTER` writer - Set this bit then clear this bit to reset the internal axi_rd FSM."]
12pub type AXIM_RST_RD_INTER_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ARB_PRI_DIS` reader - Set this bit to disable priority arbitration function."]
14pub type ARB_PRI_DIS_R = crate::BitReader;
15#[doc = "Field `ARB_PRI_DIS` writer - Set this bit to disable priority arbitration function."]
16pub type ARB_PRI_DIS_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `CLK_EN` reader - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
18pub type CLK_EN_R = crate::BitReader;
19#[doc = "Field `CLK_EN` writer - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
20pub type CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21impl R {
22    #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal axi_wr FSM."]
23    #[inline(always)]
24    pub fn axim_rst_wr_inter(&self) -> AXIM_RST_WR_INTER_R {
25        AXIM_RST_WR_INTER_R::new((self.bits & 1) != 0)
26    }
27    #[doc = "Bit 1 - Set this bit then clear this bit to reset the internal axi_rd FSM."]
28    #[inline(always)]
29    pub fn axim_rst_rd_inter(&self) -> AXIM_RST_RD_INTER_R {
30        AXIM_RST_RD_INTER_R::new(((self.bits >> 1) & 1) != 0)
31    }
32    #[doc = "Bit 3 - Set this bit to disable priority arbitration function."]
33    #[inline(always)]
34    pub fn arb_pri_dis(&self) -> ARB_PRI_DIS_R {
35        ARB_PRI_DIS_R::new(((self.bits >> 3) & 1) != 0)
36    }
37    #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
38    #[inline(always)]
39    pub fn clk_en(&self) -> CLK_EN_R {
40        CLK_EN_R::new(((self.bits >> 4) & 1) != 0)
41    }
42}
43#[cfg(feature = "impl-register-debug")]
44impl core::fmt::Debug for R {
45    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
46        f.debug_struct("MISC_CONF")
47            .field(
48                "axim_rst_wr_inter",
49                &format_args!("{}", self.axim_rst_wr_inter().bit()),
50            )
51            .field(
52                "axim_rst_rd_inter",
53                &format_args!("{}", self.axim_rst_rd_inter().bit()),
54            )
55            .field("arb_pri_dis", &format_args!("{}", self.arb_pri_dis().bit()))
56            .field("clk_en", &format_args!("{}", self.clk_en().bit()))
57            .finish()
58    }
59}
60#[cfg(feature = "impl-register-debug")]
61impl core::fmt::Debug for crate::generic::Reg<MISC_CONF_SPEC> {
62    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
63        core::fmt::Debug::fmt(&self.read(), f)
64    }
65}
66impl W {
67    #[doc = "Bit 0 - Set this bit then clear this bit to reset the internal axi_wr FSM."]
68    #[inline(always)]
69    #[must_use]
70    pub fn axim_rst_wr_inter(&mut self) -> AXIM_RST_WR_INTER_W<MISC_CONF_SPEC> {
71        AXIM_RST_WR_INTER_W::new(self, 0)
72    }
73    #[doc = "Bit 1 - Set this bit then clear this bit to reset the internal axi_rd FSM."]
74    #[inline(always)]
75    #[must_use]
76    pub fn axim_rst_rd_inter(&mut self) -> AXIM_RST_RD_INTER_W<MISC_CONF_SPEC> {
77        AXIM_RST_RD_INTER_W::new(self, 1)
78    }
79    #[doc = "Bit 3 - Set this bit to disable priority arbitration function."]
80    #[inline(always)]
81    #[must_use]
82    pub fn arb_pri_dis(&mut self) -> ARB_PRI_DIS_W<MISC_CONF_SPEC> {
83        ARB_PRI_DIS_W::new(self, 3)
84    }
85    #[doc = "Bit 4 - 1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers."]
86    #[inline(always)]
87    #[must_use]
88    pub fn clk_en(&mut self) -> CLK_EN_W<MISC_CONF_SPEC> {
89        CLK_EN_W::new(self, 4)
90    }
91}
92#[doc = "MISC register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`misc_conf::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`misc_conf::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
93pub struct MISC_CONF_SPEC;
94impl crate::RegisterSpec for MISC_CONF_SPEC {
95    type Ux = u32;
96}
97#[doc = "`read()` method returns [`misc_conf::R`](R) reader structure"]
98impl crate::Readable for MISC_CONF_SPEC {}
99#[doc = "`write(|w| ..)` method takes [`misc_conf::W`](W) writer structure"]
100impl crate::Writable for MISC_CONF_SPEC {
101    type Safety = crate::Unsafe;
102    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
103    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
104}
105#[doc = "`reset()` method sets MISC_CONF to value 0"]
106impl crate::Resettable for MISC_CONF_SPEC {
107    const RESET_VALUE: u32 = 0;
108}
esp32p4/axi_dma/misc_conf.rs

esp32p4/axi_dma/
misc_conf.rs
