esp32p4/adc/
ctrl2.rs

1#[doc = "Register `CTRL2` reader"]
2pub type R = crate::R<CTRL2_SPEC>;
3#[doc = "Register `CTRL2` writer"]
4pub type W = crate::W<CTRL2_SPEC>;
5#[doc = "Field `MEAS_NUM_LIMIT` reader - need_des"]
6pub type MEAS_NUM_LIMIT_R = crate::BitReader;
7#[doc = "Field `MEAS_NUM_LIMIT` writer - need_des"]
8pub type MEAS_NUM_LIMIT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `MAX_MEAS_NUM` reader - max conversion number"]
10pub type MAX_MEAS_NUM_R = crate::FieldReader;
11#[doc = "Field `MAX_MEAS_NUM` writer - max conversion number"]
12pub type MAX_MEAS_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
13#[doc = "Field `SAR1_INV` reader - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
14pub type SAR1_INV_R = crate::BitReader;
15#[doc = "Field `SAR1_INV` writer - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
16pub type SAR1_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SAR2_INV` reader - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
18pub type SAR2_INV_R = crate::BitReader;
19#[doc = "Field `SAR2_INV` writer - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
20pub type SAR2_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `TIMER_SEL` reader - 1: select saradc timer 0: i2s_ws trigger"]
22pub type TIMER_SEL_R = crate::BitReader;
23#[doc = "Field `TIMER_SEL` writer - 1: select saradc timer 0: i2s_ws trigger"]
24pub type TIMER_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `TIMER_TARGET` reader - to set saradc timer target"]
26pub type TIMER_TARGET_R = crate::FieldReader<u16>;
27#[doc = "Field `TIMER_TARGET` writer - to set saradc timer target"]
28pub type TIMER_TARGET_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
29#[doc = "Field `TIMER_EN` reader - to enable saradc timer trigger"]
30pub type TIMER_EN_R = crate::BitReader;
31#[doc = "Field `TIMER_EN` writer - to enable saradc timer trigger"]
32pub type TIMER_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33impl R {
34    #[doc = "Bit 0 - need_des"]
35    #[inline(always)]
36    pub fn meas_num_limit(&self) -> MEAS_NUM_LIMIT_R {
37        MEAS_NUM_LIMIT_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bits 1:8 - max conversion number"]
40    #[inline(always)]
41    pub fn max_meas_num(&self) -> MAX_MEAS_NUM_R {
42        MAX_MEAS_NUM_R::new(((self.bits >> 1) & 0xff) as u8)
43    }
44    #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
45    #[inline(always)]
46    pub fn sar1_inv(&self) -> SAR1_INV_R {
47        SAR1_INV_R::new(((self.bits >> 9) & 1) != 0)
48    }
49    #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
50    #[inline(always)]
51    pub fn sar2_inv(&self) -> SAR2_INV_R {
52        SAR2_INV_R::new(((self.bits >> 10) & 1) != 0)
53    }
54    #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
55    #[inline(always)]
56    pub fn timer_sel(&self) -> TIMER_SEL_R {
57        TIMER_SEL_R::new(((self.bits >> 11) & 1) != 0)
58    }
59    #[doc = "Bits 12:23 - to set saradc timer target"]
60    #[inline(always)]
61    pub fn timer_target(&self) -> TIMER_TARGET_R {
62        TIMER_TARGET_R::new(((self.bits >> 12) & 0x0fff) as u16)
63    }
64    #[doc = "Bit 24 - to enable saradc timer trigger"]
65    #[inline(always)]
66    pub fn timer_en(&self) -> TIMER_EN_R {
67        TIMER_EN_R::new(((self.bits >> 24) & 1) != 0)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("CTRL2")
74            .field(
75                "meas_num_limit",
76                &format_args!("{}", self.meas_num_limit().bit()),
77            )
78            .field(
79                "max_meas_num",
80                &format_args!("{}", self.max_meas_num().bits()),
81            )
82            .field("sar1_inv", &format_args!("{}", self.sar1_inv().bit()))
83            .field("sar2_inv", &format_args!("{}", self.sar2_inv().bit()))
84            .field("timer_sel", &format_args!("{}", self.timer_sel().bit()))
85            .field(
86                "timer_target",
87                &format_args!("{}", self.timer_target().bits()),
88            )
89            .field("timer_en", &format_args!("{}", self.timer_en().bit()))
90            .finish()
91    }
92}
93#[cfg(feature = "impl-register-debug")]
94impl core::fmt::Debug for crate::generic::Reg<CTRL2_SPEC> {
95    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
96        core::fmt::Debug::fmt(&self.read(), f)
97    }
98}
99impl W {
100    #[doc = "Bit 0 - need_des"]
101    #[inline(always)]
102    #[must_use]
103    pub fn meas_num_limit(&mut self) -> MEAS_NUM_LIMIT_W<CTRL2_SPEC> {
104        MEAS_NUM_LIMIT_W::new(self, 0)
105    }
106    #[doc = "Bits 1:8 - max conversion number"]
107    #[inline(always)]
108    #[must_use]
109    pub fn max_meas_num(&mut self) -> MAX_MEAS_NUM_W<CTRL2_SPEC> {
110        MAX_MEAS_NUM_W::new(self, 1)
111    }
112    #[doc = "Bit 9 - 1: data to DIG ADC1 CTRL is inverted, otherwise not"]
113    #[inline(always)]
114    #[must_use]
115    pub fn sar1_inv(&mut self) -> SAR1_INV_W<CTRL2_SPEC> {
116        SAR1_INV_W::new(self, 9)
117    }
118    #[doc = "Bit 10 - 1: data to DIG ADC2 CTRL is inverted, otherwise not"]
119    #[inline(always)]
120    #[must_use]
121    pub fn sar2_inv(&mut self) -> SAR2_INV_W<CTRL2_SPEC> {
122        SAR2_INV_W::new(self, 10)
123    }
124    #[doc = "Bit 11 - 1: select saradc timer 0: i2s_ws trigger"]
125    #[inline(always)]
126    #[must_use]
127    pub fn timer_sel(&mut self) -> TIMER_SEL_W<CTRL2_SPEC> {
128        TIMER_SEL_W::new(self, 11)
129    }
130    #[doc = "Bits 12:23 - to set saradc timer target"]
131    #[inline(always)]
132    #[must_use]
133    pub fn timer_target(&mut self) -> TIMER_TARGET_W<CTRL2_SPEC> {
134        TIMER_TARGET_W::new(self, 12)
135    }
136    #[doc = "Bit 24 - to enable saradc timer trigger"]
137    #[inline(always)]
138    #[must_use]
139    pub fn timer_en(&mut self) -> TIMER_EN_W<CTRL2_SPEC> {
140        TIMER_EN_W::new(self, 24)
141    }
142}
143#[doc = "Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
144pub struct CTRL2_SPEC;
145impl crate::RegisterSpec for CTRL2_SPEC {
146    type Ux = u32;
147}
148#[doc = "`read()` method returns [`ctrl2::R`](R) reader structure"]
149impl crate::Readable for CTRL2_SPEC {}
150#[doc = "`write(|w| ..)` method takes [`ctrl2::W`](W) writer structure"]
151impl crate::Writable for CTRL2_SPEC {
152    type Safety = crate::Unsafe;
153    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
154    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
155}
156#[doc = "`reset()` method sets CTRL2 to value 0xa1fe"]
157impl crate::Resettable for CTRL2_SPEC {
158    const RESET_VALUE: u32 = 0xa1fe;
159}