esp32p4/uhci0/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `RX_START` writer - Set this bit to clear the raw interrupt of UHCI_RX_START_INT."]
4pub type RX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `TX_START` writer - Set this bit to clear the raw interrupt of UHCI_TX_START_INT."]
6pub type TX_START_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `RX_HUNG` writer - Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT."]
8pub type RX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `TX_HUNG` writer - Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT."]
10pub type TX_HUNG_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `SEND_S_REG_Q` writer - Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT."]
12pub type SEND_S_REG_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `SEND_A_REG_Q` writer - Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT."]
14pub type SEND_A_REG_Q_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `OUTLINK_EOF_ERR` writer - Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT."]
16pub type OUTLINK_EOF_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `APP_CTRL0` writer - Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT."]
18pub type APP_CTRL0_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `APP_CTRL1` writer - Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT."]
20pub type APP_CTRL1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[cfg(feature = "impl-register-debug")]
22impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
23    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
24        write!(f, "(not readable)")
25    }
26}
27impl W {
28    #[doc = "Bit 0 - Set this bit to clear the raw interrupt of UHCI_RX_START_INT."]
29    #[inline(always)]
30    #[must_use]
31    pub fn rx_start(&mut self) -> RX_START_W<INT_CLR_SPEC> {
32        RX_START_W::new(self, 0)
33    }
34    #[doc = "Bit 1 - Set this bit to clear the raw interrupt of UHCI_TX_START_INT."]
35    #[inline(always)]
36    #[must_use]
37    pub fn tx_start(&mut self) -> TX_START_W<INT_CLR_SPEC> {
38        TX_START_W::new(self, 1)
39    }
40    #[doc = "Bit 2 - Set this bit to clear the raw interrupt of UHCI_RX_HUNG_INT."]
41    #[inline(always)]
42    #[must_use]
43    pub fn rx_hung(&mut self) -> RX_HUNG_W<INT_CLR_SPEC> {
44        RX_HUNG_W::new(self, 2)
45    }
46    #[doc = "Bit 3 - Set this bit to clear the raw interrupt of UHCI_TX_HUNG_INT."]
47    #[inline(always)]
48    #[must_use]
49    pub fn tx_hung(&mut self) -> TX_HUNG_W<INT_CLR_SPEC> {
50        TX_HUNG_W::new(self, 3)
51    }
52    #[doc = "Bit 4 - Set this bit to clear the raw interrupt of UHCI_SEND_S_REG_Q_INT."]
53    #[inline(always)]
54    #[must_use]
55    pub fn send_s_reg_q(&mut self) -> SEND_S_REG_Q_W<INT_CLR_SPEC> {
56        SEND_S_REG_Q_W::new(self, 4)
57    }
58    #[doc = "Bit 5 - Set this bit to clear the raw interrupt of UHCI_SEND_A_REG_Q_INT."]
59    #[inline(always)]
60    #[must_use]
61    pub fn send_a_reg_q(&mut self) -> SEND_A_REG_Q_W<INT_CLR_SPEC> {
62        SEND_A_REG_Q_W::new(self, 5)
63    }
64    #[doc = "Bit 6 - Set this bit to clear the raw interrupt of UHCI_OUT_EOF_INT."]
65    #[inline(always)]
66    #[must_use]
67    pub fn outlink_eof_err(&mut self) -> OUTLINK_EOF_ERR_W<INT_CLR_SPEC> {
68        OUTLINK_EOF_ERR_W::new(self, 6)
69    }
70    #[doc = "Bit 7 - Set this bit to clear the raw interrupt of UHCI_APP_CTRL0_INT."]
71    #[inline(always)]
72    #[must_use]
73    pub fn app_ctrl0(&mut self) -> APP_CTRL0_W<INT_CLR_SPEC> {
74        APP_CTRL0_W::new(self, 7)
75    }
76    #[doc = "Bit 8 - Set this bit to clear the raw interrupt of UHCI_APP_CTRL1_INT."]
77    #[inline(always)]
78    #[must_use]
79    pub fn app_ctrl1(&mut self) -> APP_CTRL1_W<INT_CLR_SPEC> {
80        APP_CTRL1_W::new(self, 8)
81    }
82}
83#[doc = "UHCI Interrupt Clear Register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct INT_CLR_SPEC;
85impl crate::RegisterSpec for INT_CLR_SPEC {
86    type Ux = u32;
87}
88#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
89impl crate::Writable for INT_CLR_SPEC {
90    type Safety = crate::Unsafe;
91    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
92    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x01ff;
93}
94#[doc = "`reset()` method sets INT_CLR to value 0"]
95impl crate::Resettable for INT_CLR_SPEC {
96    const RESET_VALUE: u32 = 0;
97}
esp32p4/uhci0/int_clr.rs

esp32p4/uhci0/
int_clr.rs
