1#[doc = "Register `INT_ENA` reader"]
2pub type R = crate::R<INT_ENA_SPEC>;
3#[doc = "Register `INT_ENA` writer"]
4pub type W = crate::W<INT_ENA_SPEC>;
5#[doc = "Field `RXFIFO_FULL` reader - This is the enable bit for rxfifo_full_int_st register."]
6pub type RXFIFO_FULL_R = crate::BitReader;
7#[doc = "Field `RXFIFO_FULL` writer - This is the enable bit for rxfifo_full_int_st register."]
8pub type RXFIFO_FULL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `TXFIFO_EMPTY` reader - This is the enable bit for txfifo_empty_int_st register."]
10pub type TXFIFO_EMPTY_R = crate::BitReader;
11#[doc = "Field `TXFIFO_EMPTY` writer - This is the enable bit for txfifo_empty_int_st register."]
12pub type TXFIFO_EMPTY_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `PARITY_ERR` reader - This is the enable bit for parity_err_int_st register."]
14pub type PARITY_ERR_R = crate::BitReader;
15#[doc = "Field `PARITY_ERR` writer - This is the enable bit for parity_err_int_st register."]
16pub type PARITY_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FRM_ERR` reader - This is the enable bit for frm_err_int_st register."]
18pub type FRM_ERR_R = crate::BitReader;
19#[doc = "Field `FRM_ERR` writer - This is the enable bit for frm_err_int_st register."]
20pub type FRM_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `RXFIFO_OVF` reader - This is the enable bit for rxfifo_ovf_int_st register."]
22pub type RXFIFO_OVF_R = crate::BitReader;
23#[doc = "Field `RXFIFO_OVF` writer - This is the enable bit for rxfifo_ovf_int_st register."]
24pub type RXFIFO_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `DSR_CHG` reader - This is the enable bit for dsr_chg_int_st register."]
26pub type DSR_CHG_R = crate::BitReader;
27#[doc = "Field `DSR_CHG` writer - This is the enable bit for dsr_chg_int_st register."]
28pub type DSR_CHG_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `CTS_CHG` reader - This is the enable bit for cts_chg_int_st register."]
30pub type CTS_CHG_R = crate::BitReader;
31#[doc = "Field `CTS_CHG` writer - This is the enable bit for cts_chg_int_st register."]
32pub type CTS_CHG_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `BRK_DET` reader - This is the enable bit for brk_det_int_st register."]
34pub type BRK_DET_R = crate::BitReader;
35#[doc = "Field `BRK_DET` writer - This is the enable bit for brk_det_int_st register."]
36pub type BRK_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `RXFIFO_TOUT` reader - This is the enable bit for rxfifo_tout_int_st register."]
38pub type RXFIFO_TOUT_R = crate::BitReader;
39#[doc = "Field `RXFIFO_TOUT` writer - This is the enable bit for rxfifo_tout_int_st register."]
40pub type RXFIFO_TOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SW_XON` reader - This is the enable bit for sw_xon_int_st register."]
42pub type SW_XON_R = crate::BitReader;
43#[doc = "Field `SW_XON` writer - This is the enable bit for sw_xon_int_st register."]
44pub type SW_XON_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SW_XOFF` reader - This is the enable bit for sw_xoff_int_st register."]
46pub type SW_XOFF_R = crate::BitReader;
47#[doc = "Field `SW_XOFF` writer - This is the enable bit for sw_xoff_int_st register."]
48pub type SW_XOFF_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `GLITCH_DET` reader - This is the enable bit for glitch_det_int_st register."]
50pub type GLITCH_DET_R = crate::BitReader;
51#[doc = "Field `GLITCH_DET` writer - This is the enable bit for glitch_det_int_st register."]
52pub type GLITCH_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `TX_BRK_DONE` reader - This is the enable bit for tx_brk_done_int_st register."]
54pub type TX_BRK_DONE_R = crate::BitReader;
55#[doc = "Field `TX_BRK_DONE` writer - This is the enable bit for tx_brk_done_int_st register."]
56pub type TX_BRK_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `TX_BRK_IDLE_DONE` reader - This is the enable bit for tx_brk_idle_done_int_st register."]
58pub type TX_BRK_IDLE_DONE_R = crate::BitReader;
59#[doc = "Field `TX_BRK_IDLE_DONE` writer - This is the enable bit for tx_brk_idle_done_int_st register."]
60pub type TX_BRK_IDLE_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TX_DONE` reader - This is the enable bit for tx_done_int_st register."]
62pub type TX_DONE_R = crate::BitReader;
63#[doc = "Field `TX_DONE` writer - This is the enable bit for tx_done_int_st register."]
64pub type TX_DONE_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `RS485_PARITY_ERR` reader - This is the enable bit for rs485_parity_err_int_st register."]
66pub type RS485_PARITY_ERR_R = crate::BitReader;
67#[doc = "Field `RS485_PARITY_ERR` writer - This is the enable bit for rs485_parity_err_int_st register."]
68pub type RS485_PARITY_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `RS485_FRM_ERR` reader - This is the enable bit for rs485_parity_err_int_st register."]
70pub type RS485_FRM_ERR_R = crate::BitReader;
71#[doc = "Field `RS485_FRM_ERR` writer - This is the enable bit for rs485_parity_err_int_st register."]
72pub type RS485_FRM_ERR_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `RS485_CLASH` reader - This is the enable bit for rs485_clash_int_st register."]
74pub type RS485_CLASH_R = crate::BitReader;
75#[doc = "Field `RS485_CLASH` writer - This is the enable bit for rs485_clash_int_st register."]
76pub type RS485_CLASH_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `AT_CMD_CHAR_DET` reader - This is the enable bit for at_cmd_char_det_int_st register."]
78pub type AT_CMD_CHAR_DET_R = crate::BitReader;
79#[doc = "Field `AT_CMD_CHAR_DET` writer - This is the enable bit for at_cmd_char_det_int_st register."]
80pub type AT_CMD_CHAR_DET_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `WAKEUP` reader - This is the enable bit for uart_wakeup_int_st register."]
82pub type WAKEUP_R = crate::BitReader;
83#[doc = "Field `WAKEUP` writer - This is the enable bit for uart_wakeup_int_st register."]
84pub type WAKEUP_W<'a, REG> = crate::BitWriter<'a, REG>;
85impl R {
86 #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
87 #[inline(always)]
88 pub fn rxfifo_full(&self) -> RXFIFO_FULL_R {
89 RXFIFO_FULL_R::new((self.bits & 1) != 0)
90 }
91 #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."]
92 #[inline(always)]
93 pub fn txfifo_empty(&self) -> TXFIFO_EMPTY_R {
94 TXFIFO_EMPTY_R::new(((self.bits >> 1) & 1) != 0)
95 }
96 #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."]
97 #[inline(always)]
98 pub fn parity_err(&self) -> PARITY_ERR_R {
99 PARITY_ERR_R::new(((self.bits >> 2) & 1) != 0)
100 }
101 #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."]
102 #[inline(always)]
103 pub fn frm_err(&self) -> FRM_ERR_R {
104 FRM_ERR_R::new(((self.bits >> 3) & 1) != 0)
105 }
106 #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."]
107 #[inline(always)]
108 pub fn rxfifo_ovf(&self) -> RXFIFO_OVF_R {
109 RXFIFO_OVF_R::new(((self.bits >> 4) & 1) != 0)
110 }
111 #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."]
112 #[inline(always)]
113 pub fn dsr_chg(&self) -> DSR_CHG_R {
114 DSR_CHG_R::new(((self.bits >> 5) & 1) != 0)
115 }
116 #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."]
117 #[inline(always)]
118 pub fn cts_chg(&self) -> CTS_CHG_R {
119 CTS_CHG_R::new(((self.bits >> 6) & 1) != 0)
120 }
121 #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."]
122 #[inline(always)]
123 pub fn brk_det(&self) -> BRK_DET_R {
124 BRK_DET_R::new(((self.bits >> 7) & 1) != 0)
125 }
126 #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."]
127 #[inline(always)]
128 pub fn rxfifo_tout(&self) -> RXFIFO_TOUT_R {
129 RXFIFO_TOUT_R::new(((self.bits >> 8) & 1) != 0)
130 }
131 #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."]
132 #[inline(always)]
133 pub fn sw_xon(&self) -> SW_XON_R {
134 SW_XON_R::new(((self.bits >> 9) & 1) != 0)
135 }
136 #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."]
137 #[inline(always)]
138 pub fn sw_xoff(&self) -> SW_XOFF_R {
139 SW_XOFF_R::new(((self.bits >> 10) & 1) != 0)
140 }
141 #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."]
142 #[inline(always)]
143 pub fn glitch_det(&self) -> GLITCH_DET_R {
144 GLITCH_DET_R::new(((self.bits >> 11) & 1) != 0)
145 }
146 #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."]
147 #[inline(always)]
148 pub fn tx_brk_done(&self) -> TX_BRK_DONE_R {
149 TX_BRK_DONE_R::new(((self.bits >> 12) & 1) != 0)
150 }
151 #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."]
152 #[inline(always)]
153 pub fn tx_brk_idle_done(&self) -> TX_BRK_IDLE_DONE_R {
154 TX_BRK_IDLE_DONE_R::new(((self.bits >> 13) & 1) != 0)
155 }
156 #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."]
157 #[inline(always)]
158 pub fn tx_done(&self) -> TX_DONE_R {
159 TX_DONE_R::new(((self.bits >> 14) & 1) != 0)
160 }
161 #[doc = "Bit 15 - This is the enable bit for rs485_parity_err_int_st register."]
162 #[inline(always)]
163 pub fn rs485_parity_err(&self) -> RS485_PARITY_ERR_R {
164 RS485_PARITY_ERR_R::new(((self.bits >> 15) & 1) != 0)
165 }
166 #[doc = "Bit 16 - This is the enable bit for rs485_parity_err_int_st register."]
167 #[inline(always)]
168 pub fn rs485_frm_err(&self) -> RS485_FRM_ERR_R {
169 RS485_FRM_ERR_R::new(((self.bits >> 16) & 1) != 0)
170 }
171 #[doc = "Bit 17 - This is the enable bit for rs485_clash_int_st register."]
172 #[inline(always)]
173 pub fn rs485_clash(&self) -> RS485_CLASH_R {
174 RS485_CLASH_R::new(((self.bits >> 17) & 1) != 0)
175 }
176 #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."]
177 #[inline(always)]
178 pub fn at_cmd_char_det(&self) -> AT_CMD_CHAR_DET_R {
179 AT_CMD_CHAR_DET_R::new(((self.bits >> 18) & 1) != 0)
180 }
181 #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."]
182 #[inline(always)]
183 pub fn wakeup(&self) -> WAKEUP_R {
184 WAKEUP_R::new(((self.bits >> 19) & 1) != 0)
185 }
186}
187#[cfg(feature = "impl-register-debug")]
188impl core::fmt::Debug for R {
189 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
190 f.debug_struct("INT_ENA")
191 .field("rxfifo_full", &format_args!("{}", self.rxfifo_full().bit()))
192 .field(
193 "txfifo_empty",
194 &format_args!("{}", self.txfifo_empty().bit()),
195 )
196 .field("parity_err", &format_args!("{}", self.parity_err().bit()))
197 .field("frm_err", &format_args!("{}", self.frm_err().bit()))
198 .field("rxfifo_ovf", &format_args!("{}", self.rxfifo_ovf().bit()))
199 .field("dsr_chg", &format_args!("{}", self.dsr_chg().bit()))
200 .field("cts_chg", &format_args!("{}", self.cts_chg().bit()))
201 .field("brk_det", &format_args!("{}", self.brk_det().bit()))
202 .field("rxfifo_tout", &format_args!("{}", self.rxfifo_tout().bit()))
203 .field("sw_xon", &format_args!("{}", self.sw_xon().bit()))
204 .field("sw_xoff", &format_args!("{}", self.sw_xoff().bit()))
205 .field("glitch_det", &format_args!("{}", self.glitch_det().bit()))
206 .field("tx_brk_done", &format_args!("{}", self.tx_brk_done().bit()))
207 .field(
208 "tx_brk_idle_done",
209 &format_args!("{}", self.tx_brk_idle_done().bit()),
210 )
211 .field("tx_done", &format_args!("{}", self.tx_done().bit()))
212 .field(
213 "rs485_parity_err",
214 &format_args!("{}", self.rs485_parity_err().bit()),
215 )
216 .field(
217 "rs485_frm_err",
218 &format_args!("{}", self.rs485_frm_err().bit()),
219 )
220 .field("rs485_clash", &format_args!("{}", self.rs485_clash().bit()))
221 .field(
222 "at_cmd_char_det",
223 &format_args!("{}", self.at_cmd_char_det().bit()),
224 )
225 .field("wakeup", &format_args!("{}", self.wakeup().bit()))
226 .finish()
227 }
228}
229#[cfg(feature = "impl-register-debug")]
230impl core::fmt::Debug for crate::generic::Reg<INT_ENA_SPEC> {
231 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
232 core::fmt::Debug::fmt(&self.read(), f)
233 }
234}
235impl W {
236 #[doc = "Bit 0 - This is the enable bit for rxfifo_full_int_st register."]
237 #[inline(always)]
238 #[must_use]
239 pub fn rxfifo_full(&mut self) -> RXFIFO_FULL_W<INT_ENA_SPEC> {
240 RXFIFO_FULL_W::new(self, 0)
241 }
242 #[doc = "Bit 1 - This is the enable bit for txfifo_empty_int_st register."]
243 #[inline(always)]
244 #[must_use]
245 pub fn txfifo_empty(&mut self) -> TXFIFO_EMPTY_W<INT_ENA_SPEC> {
246 TXFIFO_EMPTY_W::new(self, 1)
247 }
248 #[doc = "Bit 2 - This is the enable bit for parity_err_int_st register."]
249 #[inline(always)]
250 #[must_use]
251 pub fn parity_err(&mut self) -> PARITY_ERR_W<INT_ENA_SPEC> {
252 PARITY_ERR_W::new(self, 2)
253 }
254 #[doc = "Bit 3 - This is the enable bit for frm_err_int_st register."]
255 #[inline(always)]
256 #[must_use]
257 pub fn frm_err(&mut self) -> FRM_ERR_W<INT_ENA_SPEC> {
258 FRM_ERR_W::new(self, 3)
259 }
260 #[doc = "Bit 4 - This is the enable bit for rxfifo_ovf_int_st register."]
261 #[inline(always)]
262 #[must_use]
263 pub fn rxfifo_ovf(&mut self) -> RXFIFO_OVF_W<INT_ENA_SPEC> {
264 RXFIFO_OVF_W::new(self, 4)
265 }
266 #[doc = "Bit 5 - This is the enable bit for dsr_chg_int_st register."]
267 #[inline(always)]
268 #[must_use]
269 pub fn dsr_chg(&mut self) -> DSR_CHG_W<INT_ENA_SPEC> {
270 DSR_CHG_W::new(self, 5)
271 }
272 #[doc = "Bit 6 - This is the enable bit for cts_chg_int_st register."]
273 #[inline(always)]
274 #[must_use]
275 pub fn cts_chg(&mut self) -> CTS_CHG_W<INT_ENA_SPEC> {
276 CTS_CHG_W::new(self, 6)
277 }
278 #[doc = "Bit 7 - This is the enable bit for brk_det_int_st register."]
279 #[inline(always)]
280 #[must_use]
281 pub fn brk_det(&mut self) -> BRK_DET_W<INT_ENA_SPEC> {
282 BRK_DET_W::new(self, 7)
283 }
284 #[doc = "Bit 8 - This is the enable bit for rxfifo_tout_int_st register."]
285 #[inline(always)]
286 #[must_use]
287 pub fn rxfifo_tout(&mut self) -> RXFIFO_TOUT_W<INT_ENA_SPEC> {
288 RXFIFO_TOUT_W::new(self, 8)
289 }
290 #[doc = "Bit 9 - This is the enable bit for sw_xon_int_st register."]
291 #[inline(always)]
292 #[must_use]
293 pub fn sw_xon(&mut self) -> SW_XON_W<INT_ENA_SPEC> {
294 SW_XON_W::new(self, 9)
295 }
296 #[doc = "Bit 10 - This is the enable bit for sw_xoff_int_st register."]
297 #[inline(always)]
298 #[must_use]
299 pub fn sw_xoff(&mut self) -> SW_XOFF_W<INT_ENA_SPEC> {
300 SW_XOFF_W::new(self, 10)
301 }
302 #[doc = "Bit 11 - This is the enable bit for glitch_det_int_st register."]
303 #[inline(always)]
304 #[must_use]
305 pub fn glitch_det(&mut self) -> GLITCH_DET_W<INT_ENA_SPEC> {
306 GLITCH_DET_W::new(self, 11)
307 }
308 #[doc = "Bit 12 - This is the enable bit for tx_brk_done_int_st register."]
309 #[inline(always)]
310 #[must_use]
311 pub fn tx_brk_done(&mut self) -> TX_BRK_DONE_W<INT_ENA_SPEC> {
312 TX_BRK_DONE_W::new(self, 12)
313 }
314 #[doc = "Bit 13 - This is the enable bit for tx_brk_idle_done_int_st register."]
315 #[inline(always)]
316 #[must_use]
317 pub fn tx_brk_idle_done(&mut self) -> TX_BRK_IDLE_DONE_W<INT_ENA_SPEC> {
318 TX_BRK_IDLE_DONE_W::new(self, 13)
319 }
320 #[doc = "Bit 14 - This is the enable bit for tx_done_int_st register."]
321 #[inline(always)]
322 #[must_use]
323 pub fn tx_done(&mut self) -> TX_DONE_W<INT_ENA_SPEC> {
324 TX_DONE_W::new(self, 14)
325 }
326 #[doc = "Bit 15 - This is the enable bit for rs485_parity_err_int_st register."]
327 #[inline(always)]
328 #[must_use]
329 pub fn rs485_parity_err(&mut self) -> RS485_PARITY_ERR_W<INT_ENA_SPEC> {
330 RS485_PARITY_ERR_W::new(self, 15)
331 }
332 #[doc = "Bit 16 - This is the enable bit for rs485_parity_err_int_st register."]
333 #[inline(always)]
334 #[must_use]
335 pub fn rs485_frm_err(&mut self) -> RS485_FRM_ERR_W<INT_ENA_SPEC> {
336 RS485_FRM_ERR_W::new(self, 16)
337 }
338 #[doc = "Bit 17 - This is the enable bit for rs485_clash_int_st register."]
339 #[inline(always)]
340 #[must_use]
341 pub fn rs485_clash(&mut self) -> RS485_CLASH_W<INT_ENA_SPEC> {
342 RS485_CLASH_W::new(self, 17)
343 }
344 #[doc = "Bit 18 - This is the enable bit for at_cmd_char_det_int_st register."]
345 #[inline(always)]
346 #[must_use]
347 pub fn at_cmd_char_det(&mut self) -> AT_CMD_CHAR_DET_W<INT_ENA_SPEC> {
348 AT_CMD_CHAR_DET_W::new(self, 18)
349 }
350 #[doc = "Bit 19 - This is the enable bit for uart_wakeup_int_st register."]
351 #[inline(always)]
352 #[must_use]
353 pub fn wakeup(&mut self) -> WAKEUP_W<INT_ENA_SPEC> {
354 WAKEUP_W::new(self, 19)
355 }
356}
357#[doc = "Interrupt enable bits\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_ena::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_ena::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
358pub struct INT_ENA_SPEC;
359impl crate::RegisterSpec for INT_ENA_SPEC {
360 type Ux = u32;
361}
362#[doc = "`read()` method returns [`int_ena::R`](R) reader structure"]
363impl crate::Readable for INT_ENA_SPEC {}
364#[doc = "`write(|w| ..)` method takes [`int_ena::W`](W) writer structure"]
365impl crate::Writable for INT_ENA_SPEC {
366 type Safety = crate::Unsafe;
367 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
368 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
369}
370#[doc = "`reset()` method sets INT_ENA to value 0"]
371impl crate::Resettable for INT_ENA_SPEC {
372 const RESET_VALUE: u32 = 0;
373}