1#[doc = "Register `CONF0` reader"]
2pub type R = crate::R<CONF0_SPEC>;
3#[doc = "Register `CONF0` writer"]
4pub type W = crate::W<CONF0_SPEC>;
5#[doc = "Field `PARITY` reader - This register is used to configure the parity check mode."]
6pub type PARITY_R = crate::BitReader;
7#[doc = "Field `PARITY` writer - This register is used to configure the parity check mode."]
8pub type PARITY_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `PARITY_EN` reader - Set this bit to enable uart parity check."]
10pub type PARITY_EN_R = crate::BitReader;
11#[doc = "Field `PARITY_EN` writer - Set this bit to enable uart parity check."]
12pub type PARITY_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `BIT_NUM` reader - This register is used to set the length of data."]
14pub type BIT_NUM_R = crate::FieldReader;
15#[doc = "Field `BIT_NUM` writer - This register is used to set the length of data."]
16pub type BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17#[doc = "Field `STOP_BIT_NUM` reader - This register is used to set the length of stop bit."]
18pub type STOP_BIT_NUM_R = crate::FieldReader;
19#[doc = "Field `STOP_BIT_NUM` writer - This register is used to set the length of stop bit."]
20pub type STOP_BIT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `TXD_BRK` reader - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
22pub type TXD_BRK_R = crate::BitReader;
23#[doc = "Field `TXD_BRK` writer - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
24pub type TXD_BRK_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `IRDA_DPLX` reader - Set this bit to enable IrDA loopback mode."]
26pub type IRDA_DPLX_R = crate::BitReader;
27#[doc = "Field `IRDA_DPLX` writer - Set this bit to enable IrDA loopback mode."]
28pub type IRDA_DPLX_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `IRDA_TX_EN` reader - This is the start enable bit for IrDA transmitter."]
30pub type IRDA_TX_EN_R = crate::BitReader;
31#[doc = "Field `IRDA_TX_EN` writer - This is the start enable bit for IrDA transmitter."]
32pub type IRDA_TX_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `IRDA_WCTL` reader - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
34pub type IRDA_WCTL_R = crate::BitReader;
35#[doc = "Field `IRDA_WCTL` writer - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
36pub type IRDA_WCTL_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `IRDA_TX_INV` reader - Set this bit to invert the level of IrDA transmitter."]
38pub type IRDA_TX_INV_R = crate::BitReader;
39#[doc = "Field `IRDA_TX_INV` writer - Set this bit to invert the level of IrDA transmitter."]
40pub type IRDA_TX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `IRDA_RX_INV` reader - Set this bit to invert the level of IrDA receiver."]
42pub type IRDA_RX_INV_R = crate::BitReader;
43#[doc = "Field `IRDA_RX_INV` writer - Set this bit to invert the level of IrDA receiver."]
44pub type IRDA_RX_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `LOOPBACK` reader - Set this bit to enable uart loopback test mode."]
46pub type LOOPBACK_R = crate::BitReader;
47#[doc = "Field `LOOPBACK` writer - Set this bit to enable uart loopback test mode."]
48pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `TX_FLOW_EN` reader - Set this bit to enable flow control function for transmitter."]
50pub type TX_FLOW_EN_R = crate::BitReader;
51#[doc = "Field `TX_FLOW_EN` writer - Set this bit to enable flow control function for transmitter."]
52pub type TX_FLOW_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `IRDA_EN` reader - Set this bit to enable IrDA protocol."]
54pub type IRDA_EN_R = crate::BitReader;
55#[doc = "Field `IRDA_EN` writer - Set this bit to enable IrDA protocol."]
56pub type IRDA_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `RXD_INV` reader - Set this bit to inverse the level value of uart rxd signal."]
58pub type RXD_INV_R = crate::BitReader;
59#[doc = "Field `RXD_INV` writer - Set this bit to inverse the level value of uart rxd signal."]
60pub type RXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `TXD_INV` reader - Set this bit to inverse the level value of uart txd signal."]
62pub type TXD_INV_R = crate::BitReader;
63#[doc = "Field `TXD_INV` writer - Set this bit to inverse the level value of uart txd signal."]
64pub type TXD_INV_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `DIS_RX_DAT_OVF` reader - Disable UART Rx data overflow detect."]
66pub type DIS_RX_DAT_OVF_R = crate::BitReader;
67#[doc = "Field `DIS_RX_DAT_OVF` writer - Disable UART Rx data overflow detect."]
68pub type DIS_RX_DAT_OVF_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `ERR_WR_MASK` reader - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
70pub type ERR_WR_MASK_R = crate::BitReader;
71#[doc = "Field `ERR_WR_MASK` writer - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
72pub type ERR_WR_MASK_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `AUTOBAUD_EN` reader - This is the enable bit for detecting baudrate."]
74pub type AUTOBAUD_EN_R = crate::BitReader;
75#[doc = "Field `AUTOBAUD_EN` writer - This is the enable bit for detecting baudrate."]
76pub type AUTOBAUD_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `MEM_CLK_EN` reader - UART memory clock gate enable signal."]
78pub type MEM_CLK_EN_R = crate::BitReader;
79#[doc = "Field `MEM_CLK_EN` writer - UART memory clock gate enable signal."]
80pub type MEM_CLK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
81#[doc = "Field `SW_RTS` reader - This register is used to configure the software rts signal which is used in software flow control."]
82pub type SW_RTS_R = crate::BitReader;
83#[doc = "Field `SW_RTS` writer - This register is used to configure the software rts signal which is used in software flow control."]
84pub type SW_RTS_W<'a, REG> = crate::BitWriter<'a, REG>;
85#[doc = "Field `RXFIFO_RST` reader - Set this bit to reset the uart receive-FIFO."]
86pub type RXFIFO_RST_R = crate::BitReader;
87#[doc = "Field `RXFIFO_RST` writer - Set this bit to reset the uart receive-FIFO."]
88pub type RXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
89#[doc = "Field `TXFIFO_RST` reader - Set this bit to reset the uart transmit-FIFO."]
90pub type TXFIFO_RST_R = crate::BitReader;
91#[doc = "Field `TXFIFO_RST` writer - Set this bit to reset the uart transmit-FIFO."]
92pub type TXFIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
93impl R {
94 #[doc = "Bit 0 - This register is used to configure the parity check mode."]
95 #[inline(always)]
96 pub fn parity(&self) -> PARITY_R {
97 PARITY_R::new((self.bits & 1) != 0)
98 }
99 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
100 #[inline(always)]
101 pub fn parity_en(&self) -> PARITY_EN_R {
102 PARITY_EN_R::new(((self.bits >> 1) & 1) != 0)
103 }
104 #[doc = "Bits 2:3 - This register is used to set the length of data."]
105 #[inline(always)]
106 pub fn bit_num(&self) -> BIT_NUM_R {
107 BIT_NUM_R::new(((self.bits >> 2) & 3) as u8)
108 }
109 #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
110 #[inline(always)]
111 pub fn stop_bit_num(&self) -> STOP_BIT_NUM_R {
112 STOP_BIT_NUM_R::new(((self.bits >> 4) & 3) as u8)
113 }
114 #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
115 #[inline(always)]
116 pub fn txd_brk(&self) -> TXD_BRK_R {
117 TXD_BRK_R::new(((self.bits >> 6) & 1) != 0)
118 }
119 #[doc = "Bit 7 - Set this bit to enable IrDA loopback mode."]
120 #[inline(always)]
121 pub fn irda_dplx(&self) -> IRDA_DPLX_R {
122 IRDA_DPLX_R::new(((self.bits >> 7) & 1) != 0)
123 }
124 #[doc = "Bit 8 - This is the start enable bit for IrDA transmitter."]
125 #[inline(always)]
126 pub fn irda_tx_en(&self) -> IRDA_TX_EN_R {
127 IRDA_TX_EN_R::new(((self.bits >> 8) & 1) != 0)
128 }
129 #[doc = "Bit 9 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
130 #[inline(always)]
131 pub fn irda_wctl(&self) -> IRDA_WCTL_R {
132 IRDA_WCTL_R::new(((self.bits >> 9) & 1) != 0)
133 }
134 #[doc = "Bit 10 - Set this bit to invert the level of IrDA transmitter."]
135 #[inline(always)]
136 pub fn irda_tx_inv(&self) -> IRDA_TX_INV_R {
137 IRDA_TX_INV_R::new(((self.bits >> 10) & 1) != 0)
138 }
139 #[doc = "Bit 11 - Set this bit to invert the level of IrDA receiver."]
140 #[inline(always)]
141 pub fn irda_rx_inv(&self) -> IRDA_RX_INV_R {
142 IRDA_RX_INV_R::new(((self.bits >> 11) & 1) != 0)
143 }
144 #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."]
145 #[inline(always)]
146 pub fn loopback(&self) -> LOOPBACK_R {
147 LOOPBACK_R::new(((self.bits >> 12) & 1) != 0)
148 }
149 #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."]
150 #[inline(always)]
151 pub fn tx_flow_en(&self) -> TX_FLOW_EN_R {
152 TX_FLOW_EN_R::new(((self.bits >> 13) & 1) != 0)
153 }
154 #[doc = "Bit 14 - Set this bit to enable IrDA protocol."]
155 #[inline(always)]
156 pub fn irda_en(&self) -> IRDA_EN_R {
157 IRDA_EN_R::new(((self.bits >> 14) & 1) != 0)
158 }
159 #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."]
160 #[inline(always)]
161 pub fn rxd_inv(&self) -> RXD_INV_R {
162 RXD_INV_R::new(((self.bits >> 15) & 1) != 0)
163 }
164 #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."]
165 #[inline(always)]
166 pub fn txd_inv(&self) -> TXD_INV_R {
167 TXD_INV_R::new(((self.bits >> 16) & 1) != 0)
168 }
169 #[doc = "Bit 17 - Disable UART Rx data overflow detect."]
170 #[inline(always)]
171 pub fn dis_rx_dat_ovf(&self) -> DIS_RX_DAT_OVF_R {
172 DIS_RX_DAT_OVF_R::new(((self.bits >> 17) & 1) != 0)
173 }
174 #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
175 #[inline(always)]
176 pub fn err_wr_mask(&self) -> ERR_WR_MASK_R {
177 ERR_WR_MASK_R::new(((self.bits >> 18) & 1) != 0)
178 }
179 #[doc = "Bit 19 - This is the enable bit for detecting baudrate."]
180 #[inline(always)]
181 pub fn autobaud_en(&self) -> AUTOBAUD_EN_R {
182 AUTOBAUD_EN_R::new(((self.bits >> 19) & 1) != 0)
183 }
184 #[doc = "Bit 20 - UART memory clock gate enable signal."]
185 #[inline(always)]
186 pub fn mem_clk_en(&self) -> MEM_CLK_EN_R {
187 MEM_CLK_EN_R::new(((self.bits >> 20) & 1) != 0)
188 }
189 #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."]
190 #[inline(always)]
191 pub fn sw_rts(&self) -> SW_RTS_R {
192 SW_RTS_R::new(((self.bits >> 21) & 1) != 0)
193 }
194 #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."]
195 #[inline(always)]
196 pub fn rxfifo_rst(&self) -> RXFIFO_RST_R {
197 RXFIFO_RST_R::new(((self.bits >> 22) & 1) != 0)
198 }
199 #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."]
200 #[inline(always)]
201 pub fn txfifo_rst(&self) -> TXFIFO_RST_R {
202 TXFIFO_RST_R::new(((self.bits >> 23) & 1) != 0)
203 }
204}
205#[cfg(feature = "impl-register-debug")]
206impl core::fmt::Debug for R {
207 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
208 f.debug_struct("CONF0")
209 .field("parity", &format_args!("{}", self.parity().bit()))
210 .field("parity_en", &format_args!("{}", self.parity_en().bit()))
211 .field("bit_num", &format_args!("{}", self.bit_num().bits()))
212 .field(
213 "stop_bit_num",
214 &format_args!("{}", self.stop_bit_num().bits()),
215 )
216 .field("txd_brk", &format_args!("{}", self.txd_brk().bit()))
217 .field("irda_dplx", &format_args!("{}", self.irda_dplx().bit()))
218 .field("irda_tx_en", &format_args!("{}", self.irda_tx_en().bit()))
219 .field("irda_wctl", &format_args!("{}", self.irda_wctl().bit()))
220 .field("irda_tx_inv", &format_args!("{}", self.irda_tx_inv().bit()))
221 .field("irda_rx_inv", &format_args!("{}", self.irda_rx_inv().bit()))
222 .field("loopback", &format_args!("{}", self.loopback().bit()))
223 .field("tx_flow_en", &format_args!("{}", self.tx_flow_en().bit()))
224 .field("irda_en", &format_args!("{}", self.irda_en().bit()))
225 .field("rxd_inv", &format_args!("{}", self.rxd_inv().bit()))
226 .field("txd_inv", &format_args!("{}", self.txd_inv().bit()))
227 .field(
228 "dis_rx_dat_ovf",
229 &format_args!("{}", self.dis_rx_dat_ovf().bit()),
230 )
231 .field("err_wr_mask", &format_args!("{}", self.err_wr_mask().bit()))
232 .field("autobaud_en", &format_args!("{}", self.autobaud_en().bit()))
233 .field("mem_clk_en", &format_args!("{}", self.mem_clk_en().bit()))
234 .field("sw_rts", &format_args!("{}", self.sw_rts().bit()))
235 .field("rxfifo_rst", &format_args!("{}", self.rxfifo_rst().bit()))
236 .field("txfifo_rst", &format_args!("{}", self.txfifo_rst().bit()))
237 .finish()
238 }
239}
240#[cfg(feature = "impl-register-debug")]
241impl core::fmt::Debug for crate::generic::Reg<CONF0_SPEC> {
242 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
243 core::fmt::Debug::fmt(&self.read(), f)
244 }
245}
246impl W {
247 #[doc = "Bit 0 - This register is used to configure the parity check mode."]
248 #[inline(always)]
249 #[must_use]
250 pub fn parity(&mut self) -> PARITY_W<CONF0_SPEC> {
251 PARITY_W::new(self, 0)
252 }
253 #[doc = "Bit 1 - Set this bit to enable uart parity check."]
254 #[inline(always)]
255 #[must_use]
256 pub fn parity_en(&mut self) -> PARITY_EN_W<CONF0_SPEC> {
257 PARITY_EN_W::new(self, 1)
258 }
259 #[doc = "Bits 2:3 - This register is used to set the length of data."]
260 #[inline(always)]
261 #[must_use]
262 pub fn bit_num(&mut self) -> BIT_NUM_W<CONF0_SPEC> {
263 BIT_NUM_W::new(self, 2)
264 }
265 #[doc = "Bits 4:5 - This register is used to set the length of stop bit."]
266 #[inline(always)]
267 #[must_use]
268 pub fn stop_bit_num(&mut self) -> STOP_BIT_NUM_W<CONF0_SPEC> {
269 STOP_BIT_NUM_W::new(self, 4)
270 }
271 #[doc = "Bit 6 - Set this bit to enbale transmitter to send NULL when the process of sending data is done."]
272 #[inline(always)]
273 #[must_use]
274 pub fn txd_brk(&mut self) -> TXD_BRK_W<CONF0_SPEC> {
275 TXD_BRK_W::new(self, 6)
276 }
277 #[doc = "Bit 7 - Set this bit to enable IrDA loopback mode."]
278 #[inline(always)]
279 #[must_use]
280 pub fn irda_dplx(&mut self) -> IRDA_DPLX_W<CONF0_SPEC> {
281 IRDA_DPLX_W::new(self, 7)
282 }
283 #[doc = "Bit 8 - This is the start enable bit for IrDA transmitter."]
284 #[inline(always)]
285 #[must_use]
286 pub fn irda_tx_en(&mut self) -> IRDA_TX_EN_W<CONF0_SPEC> {
287 IRDA_TX_EN_W::new(self, 8)
288 }
289 #[doc = "Bit 9 - 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0."]
290 #[inline(always)]
291 #[must_use]
292 pub fn irda_wctl(&mut self) -> IRDA_WCTL_W<CONF0_SPEC> {
293 IRDA_WCTL_W::new(self, 9)
294 }
295 #[doc = "Bit 10 - Set this bit to invert the level of IrDA transmitter."]
296 #[inline(always)]
297 #[must_use]
298 pub fn irda_tx_inv(&mut self) -> IRDA_TX_INV_W<CONF0_SPEC> {
299 IRDA_TX_INV_W::new(self, 10)
300 }
301 #[doc = "Bit 11 - Set this bit to invert the level of IrDA receiver."]
302 #[inline(always)]
303 #[must_use]
304 pub fn irda_rx_inv(&mut self) -> IRDA_RX_INV_W<CONF0_SPEC> {
305 IRDA_RX_INV_W::new(self, 11)
306 }
307 #[doc = "Bit 12 - Set this bit to enable uart loopback test mode."]
308 #[inline(always)]
309 #[must_use]
310 pub fn loopback(&mut self) -> LOOPBACK_W<CONF0_SPEC> {
311 LOOPBACK_W::new(self, 12)
312 }
313 #[doc = "Bit 13 - Set this bit to enable flow control function for transmitter."]
314 #[inline(always)]
315 #[must_use]
316 pub fn tx_flow_en(&mut self) -> TX_FLOW_EN_W<CONF0_SPEC> {
317 TX_FLOW_EN_W::new(self, 13)
318 }
319 #[doc = "Bit 14 - Set this bit to enable IrDA protocol."]
320 #[inline(always)]
321 #[must_use]
322 pub fn irda_en(&mut self) -> IRDA_EN_W<CONF0_SPEC> {
323 IRDA_EN_W::new(self, 14)
324 }
325 #[doc = "Bit 15 - Set this bit to inverse the level value of uart rxd signal."]
326 #[inline(always)]
327 #[must_use]
328 pub fn rxd_inv(&mut self) -> RXD_INV_W<CONF0_SPEC> {
329 RXD_INV_W::new(self, 15)
330 }
331 #[doc = "Bit 16 - Set this bit to inverse the level value of uart txd signal."]
332 #[inline(always)]
333 #[must_use]
334 pub fn txd_inv(&mut self) -> TXD_INV_W<CONF0_SPEC> {
335 TXD_INV_W::new(self, 16)
336 }
337 #[doc = "Bit 17 - Disable UART Rx data overflow detect."]
338 #[inline(always)]
339 #[must_use]
340 pub fn dis_rx_dat_ovf(&mut self) -> DIS_RX_DAT_OVF_W<CONF0_SPEC> {
341 DIS_RX_DAT_OVF_W::new(self, 17)
342 }
343 #[doc = "Bit 18 - 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong."]
344 #[inline(always)]
345 #[must_use]
346 pub fn err_wr_mask(&mut self) -> ERR_WR_MASK_W<CONF0_SPEC> {
347 ERR_WR_MASK_W::new(self, 18)
348 }
349 #[doc = "Bit 19 - This is the enable bit for detecting baudrate."]
350 #[inline(always)]
351 #[must_use]
352 pub fn autobaud_en(&mut self) -> AUTOBAUD_EN_W<CONF0_SPEC> {
353 AUTOBAUD_EN_W::new(self, 19)
354 }
355 #[doc = "Bit 20 - UART memory clock gate enable signal."]
356 #[inline(always)]
357 #[must_use]
358 pub fn mem_clk_en(&mut self) -> MEM_CLK_EN_W<CONF0_SPEC> {
359 MEM_CLK_EN_W::new(self, 20)
360 }
361 #[doc = "Bit 21 - This register is used to configure the software rts signal which is used in software flow control."]
362 #[inline(always)]
363 #[must_use]
364 pub fn sw_rts(&mut self) -> SW_RTS_W<CONF0_SPEC> {
365 SW_RTS_W::new(self, 21)
366 }
367 #[doc = "Bit 22 - Set this bit to reset the uart receive-FIFO."]
368 #[inline(always)]
369 #[must_use]
370 pub fn rxfifo_rst(&mut self) -> RXFIFO_RST_W<CONF0_SPEC> {
371 RXFIFO_RST_W::new(self, 22)
372 }
373 #[doc = "Bit 23 - Set this bit to reset the uart transmit-FIFO."]
374 #[inline(always)]
375 #[must_use]
376 pub fn txfifo_rst(&mut self) -> TXFIFO_RST_W<CONF0_SPEC> {
377 TXFIFO_RST_W::new(self, 23)
378 }
379}
380#[doc = "a\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`conf0::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`conf0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
381pub struct CONF0_SPEC;
382impl crate::RegisterSpec for CONF0_SPEC {
383 type Ux = u32;
384}
385#[doc = "`read()` method returns [`conf0::R`](R) reader structure"]
386impl crate::Readable for CONF0_SPEC {}
387#[doc = "`write(|w| ..)` method takes [`conf0::W`](W) writer structure"]
388impl crate::Writable for CONF0_SPEC {
389 type Safety = crate::Unsafe;
390 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
391 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
392}
393#[doc = "`reset()` method sets CONF0 to value 0x1c"]
394impl crate::Resettable for CONF0_SPEC {
395 const RESET_VALUE: u32 = 0x1c;
396}