esp32p4/spi3/
cmd.rs

1#[doc = "Register `CMD` reader"]
2pub type R = crate::R<CMD_SPEC>;
3#[doc = "Register `CMD` writer"]
4pub type W = crate::W<CMD_SPEC>;
5#[doc = "Field `UPDATE` writer - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."]
6pub type UPDATE_W<'a, REG> = crate::BitWriter<'a, REG>;
7#[doc = "Field `USR` reader - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
8pub type USR_R = crate::BitReader;
9#[doc = "Field `USR` writer - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
10pub type USR_W<'a, REG> = crate::BitWriter<'a, REG>;
11impl R {
12    #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
13    #[inline(always)]
14    pub fn usr(&self) -> USR_R {
15        USR_R::new(((self.bits >> 24) & 1) != 0)
16    }
17}
18#[cfg(feature = "impl-register-debug")]
19impl core::fmt::Debug for R {
20    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
21        f.debug_struct("CMD")
22            .field("usr", &format_args!("{}", self.usr().bit()))
23            .finish()
24    }
25}
26#[cfg(feature = "impl-register-debug")]
27impl core::fmt::Debug for crate::generic::Reg<CMD_SPEC> {
28    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
29        core::fmt::Debug::fmt(&self.read(), f)
30    }
31}
32impl W {
33    #[doc = "Bit 23 - Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode."]
34    #[inline(always)]
35    #[must_use]
36    pub fn update(&mut self) -> UPDATE_W<CMD_SPEC> {
37        UPDATE_W::new(self, 23)
38    }
39    #[doc = "Bit 24 - User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf."]
40    #[inline(always)]
41    #[must_use]
42    pub fn usr(&mut self) -> USR_W<CMD_SPEC> {
43        USR_W::new(self, 24)
44    }
45}
46#[doc = "Command control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cmd::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cmd::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
47pub struct CMD_SPEC;
48impl crate::RegisterSpec for CMD_SPEC {
49    type Ux = u32;
50}
51#[doc = "`read()` method returns [`cmd::R`](R) reader structure"]
52impl crate::Readable for CMD_SPEC {}
53#[doc = "`write(|w| ..)` method takes [`cmd::W`](W) writer structure"]
54impl crate::Writable for CMD_SPEC {
55    type Safety = crate::Unsafe;
56    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
57    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
58}
59#[doc = "`reset()` method sets CMD to value 0"]
60impl crate::Resettable for CMD_SPEC {
61    const RESET_VALUE: u32 = 0;
62}
esp32p4/spi3/cmd.rs

esp32p4/spi3/
cmd.rs
