1#[doc = "Register `SLAVE` reader"]
2pub type R = crate::R<SLAVE_SPEC>;
3#[doc = "Register `SLAVE` writer"]
4pub type W = crate::W<SLAVE_SPEC>;
5#[doc = "Field `CLK_MODE` reader - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
6pub type CLK_MODE_R = crate::FieldReader;
7#[doc = "Field `CLK_MODE` writer - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
8pub type CLK_MODE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
9#[doc = "Field `CLK_MODE_13` reader - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
10pub type CLK_MODE_13_R = crate::BitReader;
11#[doc = "Field `CLK_MODE_13` writer - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
12pub type CLK_MODE_13_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `RSCK_DATA_OUT` reader - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
14pub type RSCK_DATA_OUT_R = crate::BitReader;
15#[doc = "Field `RSCK_DATA_OUT` writer - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
16pub type RSCK_DATA_OUT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `SLV_RDDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
18pub type SLV_RDDMA_BITLEN_EN_R = crate::BitReader;
19#[doc = "Field `SLV_RDDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
20pub type SLV_RDDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `SLV_WRDMA_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
22pub type SLV_WRDMA_BITLEN_EN_R = crate::BitReader;
23#[doc = "Field `SLV_WRDMA_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
24pub type SLV_WRDMA_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `SLV_RDBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
26pub type SLV_RDBUF_BITLEN_EN_R = crate::BitReader;
27#[doc = "Field `SLV_RDBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
28pub type SLV_RDBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `SLV_WRBUF_BITLEN_EN` reader - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
30pub type SLV_WRBUF_BITLEN_EN_R = crate::BitReader;
31#[doc = "Field `SLV_WRBUF_BITLEN_EN` writer - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
32pub type SLV_WRBUF_BITLEN_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `SLV_LAST_BYTE_STRB` reader - Represents the effective bit of the last received data byte in SPI slave FD and HD mode."]
34pub type SLV_LAST_BYTE_STRB_R = crate::FieldReader;
35#[doc = "Field `DMA_SEG_MAGIC_VALUE` reader - The magic value of BM table in master DMA seg-trans."]
36pub type DMA_SEG_MAGIC_VALUE_R = crate::FieldReader;
37#[doc = "Field `DMA_SEG_MAGIC_VALUE` writer - The magic value of BM table in master DMA seg-trans."]
38pub type DMA_SEG_MAGIC_VALUE_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
39#[doc = "Field `MODE` reader - Set SPI work mode. 1: slave mode 0: master mode."]
40pub type MODE_R = crate::BitReader;
41#[doc = "Field `MODE` writer - Set SPI work mode. 1: slave mode 0: master mode."]
42pub type MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
43#[doc = "Field `SOFT_RESET` writer - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
44pub type SOFT_RESET_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `USR_CONF` reader - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
46pub type USR_CONF_R = crate::BitReader;
47#[doc = "Field `USR_CONF` writer - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
48pub type USR_CONF_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `MST_FD_WAIT_DMA_TX_DATA` reader - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
50pub type MST_FD_WAIT_DMA_TX_DATA_R = crate::BitReader;
51#[doc = "Field `MST_FD_WAIT_DMA_TX_DATA` writer - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
52pub type MST_FD_WAIT_DMA_TX_DATA_W<'a, REG> = crate::BitWriter<'a, REG>;
53impl R {
54 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
55 #[inline(always)]
56 pub fn clk_mode(&self) -> CLK_MODE_R {
57 CLK_MODE_R::new((self.bits & 3) as u8)
58 }
59 #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
60 #[inline(always)]
61 pub fn clk_mode_13(&self) -> CLK_MODE_13_R {
62 CLK_MODE_13_R::new(((self.bits >> 2) & 1) != 0)
63 }
64 #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
65 #[inline(always)]
66 pub fn rsck_data_out(&self) -> RSCK_DATA_OUT_R {
67 RSCK_DATA_OUT_R::new(((self.bits >> 3) & 1) != 0)
68 }
69 #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
70 #[inline(always)]
71 pub fn slv_rddma_bitlen_en(&self) -> SLV_RDDMA_BITLEN_EN_R {
72 SLV_RDDMA_BITLEN_EN_R::new(((self.bits >> 8) & 1) != 0)
73 }
74 #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
75 #[inline(always)]
76 pub fn slv_wrdma_bitlen_en(&self) -> SLV_WRDMA_BITLEN_EN_R {
77 SLV_WRDMA_BITLEN_EN_R::new(((self.bits >> 9) & 1) != 0)
78 }
79 #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
80 #[inline(always)]
81 pub fn slv_rdbuf_bitlen_en(&self) -> SLV_RDBUF_BITLEN_EN_R {
82 SLV_RDBUF_BITLEN_EN_R::new(((self.bits >> 10) & 1) != 0)
83 }
84 #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
85 #[inline(always)]
86 pub fn slv_wrbuf_bitlen_en(&self) -> SLV_WRBUF_BITLEN_EN_R {
87 SLV_WRBUF_BITLEN_EN_R::new(((self.bits >> 11) & 1) != 0)
88 }
89 #[doc = "Bits 12:19 - Represents the effective bit of the last received data byte in SPI slave FD and HD mode."]
90 #[inline(always)]
91 pub fn slv_last_byte_strb(&self) -> SLV_LAST_BYTE_STRB_R {
92 SLV_LAST_BYTE_STRB_R::new(((self.bits >> 12) & 0xff) as u8)
93 }
94 #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."]
95 #[inline(always)]
96 pub fn dma_seg_magic_value(&self) -> DMA_SEG_MAGIC_VALUE_R {
97 DMA_SEG_MAGIC_VALUE_R::new(((self.bits >> 22) & 0x0f) as u8)
98 }
99 #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."]
100 #[inline(always)]
101 pub fn mode(&self) -> MODE_R {
102 MODE_R::new(((self.bits >> 26) & 1) != 0)
103 }
104 #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
105 #[inline(always)]
106 pub fn usr_conf(&self) -> USR_CONF_R {
107 USR_CONF_R::new(((self.bits >> 28) & 1) != 0)
108 }
109 #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
110 #[inline(always)]
111 pub fn mst_fd_wait_dma_tx_data(&self) -> MST_FD_WAIT_DMA_TX_DATA_R {
112 MST_FD_WAIT_DMA_TX_DATA_R::new(((self.bits >> 29) & 1) != 0)
113 }
114}
115#[cfg(feature = "impl-register-debug")]
116impl core::fmt::Debug for R {
117 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
118 f.debug_struct("SLAVE")
119 .field("clk_mode", &format_args!("{}", self.clk_mode().bits()))
120 .field("clk_mode_13", &format_args!("{}", self.clk_mode_13().bit()))
121 .field(
122 "rsck_data_out",
123 &format_args!("{}", self.rsck_data_out().bit()),
124 )
125 .field(
126 "slv_rddma_bitlen_en",
127 &format_args!("{}", self.slv_rddma_bitlen_en().bit()),
128 )
129 .field(
130 "slv_wrdma_bitlen_en",
131 &format_args!("{}", self.slv_wrdma_bitlen_en().bit()),
132 )
133 .field(
134 "slv_rdbuf_bitlen_en",
135 &format_args!("{}", self.slv_rdbuf_bitlen_en().bit()),
136 )
137 .field(
138 "slv_wrbuf_bitlen_en",
139 &format_args!("{}", self.slv_wrbuf_bitlen_en().bit()),
140 )
141 .field(
142 "slv_last_byte_strb",
143 &format_args!("{}", self.slv_last_byte_strb().bits()),
144 )
145 .field(
146 "dma_seg_magic_value",
147 &format_args!("{}", self.dma_seg_magic_value().bits()),
148 )
149 .field("mode", &format_args!("{}", self.mode().bit()))
150 .field("usr_conf", &format_args!("{}", self.usr_conf().bit()))
151 .field(
152 "mst_fd_wait_dma_tx_data",
153 &format_args!("{}", self.mst_fd_wait_dma_tx_data().bit()),
154 )
155 .finish()
156 }
157}
158#[cfg(feature = "impl-register-debug")]
159impl core::fmt::Debug for crate::generic::Reg<SLAVE_SPEC> {
160 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
161 core::fmt::Debug::fmt(&self.read(), f)
162 }
163}
164impl W {
165 #[doc = "Bits 0:1 - SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state."]
166 #[inline(always)]
167 #[must_use]
168 pub fn clk_mode(&mut self) -> CLK_MODE_W<SLAVE_SPEC> {
169 CLK_MODE_W::new(self, 0)
170 }
171 #[doc = "Bit 2 - {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B\\[0\\]/B\\[7\\]. 0: support spi clk mode 0 and 2, first edge output data B\\[1\\]/B\\[6\\]."]
172 #[inline(always)]
173 #[must_use]
174 pub fn clk_mode_13(&mut self) -> CLK_MODE_13_W<SLAVE_SPEC> {
175 CLK_MODE_13_W::new(self, 2)
176 }
177 #[doc = "Bit 3 - It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge"]
178 #[inline(always)]
179 #[must_use]
180 pub fn rsck_data_out(&mut self) -> RSCK_DATA_OUT_W<SLAVE_SPEC> {
181 RSCK_DATA_OUT_W::new(self, 3)
182 }
183 #[doc = "Bit 8 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others"]
184 #[inline(always)]
185 #[must_use]
186 pub fn slv_rddma_bitlen_en(&mut self) -> SLV_RDDMA_BITLEN_EN_W<SLAVE_SPEC> {
187 SLV_RDDMA_BITLEN_EN_W::new(self, 8)
188 }
189 #[doc = "Bit 9 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others"]
190 #[inline(always)]
191 #[must_use]
192 pub fn slv_wrdma_bitlen_en(&mut self) -> SLV_WRDMA_BITLEN_EN_W<SLAVE_SPEC> {
193 SLV_WRDMA_BITLEN_EN_W::new(self, 9)
194 }
195 #[doc = "Bit 10 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others"]
196 #[inline(always)]
197 #[must_use]
198 pub fn slv_rdbuf_bitlen_en(&mut self) -> SLV_RDBUF_BITLEN_EN_W<SLAVE_SPEC> {
199 SLV_RDBUF_BITLEN_EN_W::new(self, 10)
200 }
201 #[doc = "Bit 11 - 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others"]
202 #[inline(always)]
203 #[must_use]
204 pub fn slv_wrbuf_bitlen_en(&mut self) -> SLV_WRBUF_BITLEN_EN_W<SLAVE_SPEC> {
205 SLV_WRBUF_BITLEN_EN_W::new(self, 11)
206 }
207 #[doc = "Bits 22:25 - The magic value of BM table in master DMA seg-trans."]
208 #[inline(always)]
209 #[must_use]
210 pub fn dma_seg_magic_value(&mut self) -> DMA_SEG_MAGIC_VALUE_W<SLAVE_SPEC> {
211 DMA_SEG_MAGIC_VALUE_W::new(self, 22)
212 }
213 #[doc = "Bit 26 - Set SPI work mode. 1: slave mode 0: master mode."]
214 #[inline(always)]
215 #[must_use]
216 pub fn mode(&mut self) -> MODE_W<SLAVE_SPEC> {
217 MODE_W::new(self, 26)
218 }
219 #[doc = "Bit 27 - Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state."]
220 #[inline(always)]
221 #[must_use]
222 pub fn soft_reset(&mut self) -> SOFT_RESET_W<SLAVE_SPEC> {
223 SOFT_RESET_W::new(self, 27)
224 }
225 #[doc = "Bit 28 - 1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode."]
226 #[inline(always)]
227 #[must_use]
228 pub fn usr_conf(&mut self) -> USR_CONF_W<SLAVE_SPEC> {
229 USR_CONF_W::new(self, 28)
230 }
231 #[doc = "Bit 29 - In master full-duplex mode, 1: GP-SPI will wait DMA TX data is ready before starting SPI transfer. 0: GP-SPI does not wait DMA TX data before starting SPI transfer."]
232 #[inline(always)]
233 #[must_use]
234 pub fn mst_fd_wait_dma_tx_data(&mut self) -> MST_FD_WAIT_DMA_TX_DATA_W<SLAVE_SPEC> {
235 MST_FD_WAIT_DMA_TX_DATA_W::new(self, 29)
236 }
237}
238#[doc = "SPI slave control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`slave::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`slave::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
239pub struct SLAVE_SPEC;
240impl crate::RegisterSpec for SLAVE_SPEC {
241 type Ux = u32;
242}
243#[doc = "`read()` method returns [`slave::R`](R) reader structure"]
244impl crate::Readable for SLAVE_SPEC {}
245#[doc = "`write(|w| ..)` method takes [`slave::W`](W) writer structure"]
246impl crate::Writable for SLAVE_SPEC {
247 type Safety = crate::Unsafe;
248 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
249 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
250}
251#[doc = "`reset()` method sets SLAVE to value 0x0280_0000"]
252impl crate::Resettable for SLAVE_SPEC {
253 const RESET_VALUE: u32 = 0x0280_0000;
254}