esp32p4/spi2/
dma_int_clr.rs1#[doc = "Register `DMA_INT_CLR` writer"]
2pub type W = crate::W<DMA_INT_CLR_SPEC>;
3#[doc = "Field `DMA_INFIFO_FULL_ERR` writer - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
4pub type DMA_INFIFO_FULL_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `DMA_OUTFIFO_EMPTY_ERR` writer - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
6pub type DMA_OUTFIFO_EMPTY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `SLV_EX_QPI` writer - The clear bit for SPI slave Ex_QPI interrupt."]
8pub type SLV_EX_QPI_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `SLV_EN_QPI` writer - The clear bit for SPI slave En_QPI interrupt."]
10pub type SLV_EN_QPI_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `SLV_CMD7` writer - The clear bit for SPI slave CMD7 interrupt."]
12pub type SLV_CMD7_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `SLV_CMD8` writer - The clear bit for SPI slave CMD8 interrupt."]
14pub type SLV_CMD8_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `SLV_CMD9` writer - The clear bit for SPI slave CMD9 interrupt."]
16pub type SLV_CMD9_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `SLV_CMDA` writer - The clear bit for SPI slave CMDA interrupt."]
18pub type SLV_CMDA_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `SLV_RD_DMA_DONE` writer - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
20pub type SLV_RD_DMA_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `SLV_WR_DMA_DONE` writer - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
22pub type SLV_WR_DMA_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `SLV_RD_BUF_DONE` writer - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
24pub type SLV_RD_BUF_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `SLV_WR_BUF_DONE` writer - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
26pub type SLV_WR_BUF_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `TRANS_DONE` writer - The clear bit for SPI_TRANS_DONE_INT interrupt."]
28pub type TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `DMA_SEG_TRANS_DONE` writer - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
30pub type DMA_SEG_TRANS_DONE_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `SEG_MAGIC_ERR` writer - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
32pub type SEG_MAGIC_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `SLV_BUF_ADDR_ERR` writer - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
34pub type SLV_BUF_ADDR_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `SLV_CMD_ERR` writer - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."]
36pub type SLV_CMD_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `MST_RX_AFIFO_WFULL_ERR` writer - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
38pub type MST_RX_AFIFO_WFULL_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `MST_TX_AFIFO_REMPTY_ERR` writer - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
40pub type MST_TX_AFIFO_REMPTY_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `APP2` writer - The clear bit for SPI_APP2_INT interrupt."]
42pub type APP2_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[doc = "Field `APP1` writer - The clear bit for SPI_APP1_INT interrupt."]
44pub type APP1_W<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[cfg(feature = "impl-register-debug")]
46impl core::fmt::Debug for crate::generic::Reg<DMA_INT_CLR_SPEC> {
47 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
48 write!(f, "(not readable)")
49 }
50}
51impl W {
52 #[doc = "Bit 0 - The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt."]
53 #[inline(always)]
54 #[must_use]
55 pub fn dma_infifo_full_err(&mut self) -> DMA_INFIFO_FULL_ERR_W<DMA_INT_CLR_SPEC> {
56 DMA_INFIFO_FULL_ERR_W::new(self, 0)
57 }
58 #[doc = "Bit 1 - The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt."]
59 #[inline(always)]
60 #[must_use]
61 pub fn dma_outfifo_empty_err(&mut self) -> DMA_OUTFIFO_EMPTY_ERR_W<DMA_INT_CLR_SPEC> {
62 DMA_OUTFIFO_EMPTY_ERR_W::new(self, 1)
63 }
64 #[doc = "Bit 2 - The clear bit for SPI slave Ex_QPI interrupt."]
65 #[inline(always)]
66 #[must_use]
67 pub fn slv_ex_qpi(&mut self) -> SLV_EX_QPI_W<DMA_INT_CLR_SPEC> {
68 SLV_EX_QPI_W::new(self, 2)
69 }
70 #[doc = "Bit 3 - The clear bit for SPI slave En_QPI interrupt."]
71 #[inline(always)]
72 #[must_use]
73 pub fn slv_en_qpi(&mut self) -> SLV_EN_QPI_W<DMA_INT_CLR_SPEC> {
74 SLV_EN_QPI_W::new(self, 3)
75 }
76 #[doc = "Bit 4 - The clear bit for SPI slave CMD7 interrupt."]
77 #[inline(always)]
78 #[must_use]
79 pub fn slv_cmd7(&mut self) -> SLV_CMD7_W<DMA_INT_CLR_SPEC> {
80 SLV_CMD7_W::new(self, 4)
81 }
82 #[doc = "Bit 5 - The clear bit for SPI slave CMD8 interrupt."]
83 #[inline(always)]
84 #[must_use]
85 pub fn slv_cmd8(&mut self) -> SLV_CMD8_W<DMA_INT_CLR_SPEC> {
86 SLV_CMD8_W::new(self, 5)
87 }
88 #[doc = "Bit 6 - The clear bit for SPI slave CMD9 interrupt."]
89 #[inline(always)]
90 #[must_use]
91 pub fn slv_cmd9(&mut self) -> SLV_CMD9_W<DMA_INT_CLR_SPEC> {
92 SLV_CMD9_W::new(self, 6)
93 }
94 #[doc = "Bit 7 - The clear bit for SPI slave CMDA interrupt."]
95 #[inline(always)]
96 #[must_use]
97 pub fn slv_cmda(&mut self) -> SLV_CMDA_W<DMA_INT_CLR_SPEC> {
98 SLV_CMDA_W::new(self, 7)
99 }
100 #[doc = "Bit 8 - The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt."]
101 #[inline(always)]
102 #[must_use]
103 pub fn slv_rd_dma_done(&mut self) -> SLV_RD_DMA_DONE_W<DMA_INT_CLR_SPEC> {
104 SLV_RD_DMA_DONE_W::new(self, 8)
105 }
106 #[doc = "Bit 9 - The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt."]
107 #[inline(always)]
108 #[must_use]
109 pub fn slv_wr_dma_done(&mut self) -> SLV_WR_DMA_DONE_W<DMA_INT_CLR_SPEC> {
110 SLV_WR_DMA_DONE_W::new(self, 9)
111 }
112 #[doc = "Bit 10 - The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt."]
113 #[inline(always)]
114 #[must_use]
115 pub fn slv_rd_buf_done(&mut self) -> SLV_RD_BUF_DONE_W<DMA_INT_CLR_SPEC> {
116 SLV_RD_BUF_DONE_W::new(self, 10)
117 }
118 #[doc = "Bit 11 - The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt."]
119 #[inline(always)]
120 #[must_use]
121 pub fn slv_wr_buf_done(&mut self) -> SLV_WR_BUF_DONE_W<DMA_INT_CLR_SPEC> {
122 SLV_WR_BUF_DONE_W::new(self, 11)
123 }
124 #[doc = "Bit 12 - The clear bit for SPI_TRANS_DONE_INT interrupt."]
125 #[inline(always)]
126 #[must_use]
127 pub fn trans_done(&mut self) -> TRANS_DONE_W<DMA_INT_CLR_SPEC> {
128 TRANS_DONE_W::new(self, 12)
129 }
130 #[doc = "Bit 13 - The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt."]
131 #[inline(always)]
132 #[must_use]
133 pub fn dma_seg_trans_done(&mut self) -> DMA_SEG_TRANS_DONE_W<DMA_INT_CLR_SPEC> {
134 DMA_SEG_TRANS_DONE_W::new(self, 13)
135 }
136 #[doc = "Bit 14 - The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt."]
137 #[inline(always)]
138 #[must_use]
139 pub fn seg_magic_err(&mut self) -> SEG_MAGIC_ERR_W<DMA_INT_CLR_SPEC> {
140 SEG_MAGIC_ERR_W::new(self, 14)
141 }
142 #[doc = "Bit 15 - The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt."]
143 #[inline(always)]
144 #[must_use]
145 pub fn slv_buf_addr_err(&mut self) -> SLV_BUF_ADDR_ERR_W<DMA_INT_CLR_SPEC> {
146 SLV_BUF_ADDR_ERR_W::new(self, 15)
147 }
148 #[doc = "Bit 16 - The clear bit for SPI_SLV_CMD_ERR_INT interrupt."]
149 #[inline(always)]
150 #[must_use]
151 pub fn slv_cmd_err(&mut self) -> SLV_CMD_ERR_W<DMA_INT_CLR_SPEC> {
152 SLV_CMD_ERR_W::new(self, 16)
153 }
154 #[doc = "Bit 17 - The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt."]
155 #[inline(always)]
156 #[must_use]
157 pub fn mst_rx_afifo_wfull_err(&mut self) -> MST_RX_AFIFO_WFULL_ERR_W<DMA_INT_CLR_SPEC> {
158 MST_RX_AFIFO_WFULL_ERR_W::new(self, 17)
159 }
160 #[doc = "Bit 18 - The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt."]
161 #[inline(always)]
162 #[must_use]
163 pub fn mst_tx_afifo_rempty_err(&mut self) -> MST_TX_AFIFO_REMPTY_ERR_W<DMA_INT_CLR_SPEC> {
164 MST_TX_AFIFO_REMPTY_ERR_W::new(self, 18)
165 }
166 #[doc = "Bit 19 - The clear bit for SPI_APP2_INT interrupt."]
167 #[inline(always)]
168 #[must_use]
169 pub fn app2(&mut self) -> APP2_W<DMA_INT_CLR_SPEC> {
170 APP2_W::new(self, 19)
171 }
172 #[doc = "Bit 20 - The clear bit for SPI_APP1_INT interrupt."]
173 #[inline(always)]
174 #[must_use]
175 pub fn app1(&mut self) -> APP1_W<DMA_INT_CLR_SPEC> {
176 APP1_W::new(self, 20)
177 }
178}
179#[doc = "SPI interrupt clear register\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
180pub struct DMA_INT_CLR_SPEC;
181impl crate::RegisterSpec for DMA_INT_CLR_SPEC {
182 type Ux = u32;
183}
184#[doc = "`write(|w| ..)` method takes [`dma_int_clr::W`](W) writer structure"]
185impl crate::Writable for DMA_INT_CLR_SPEC {
186 type Safety = crate::Unsafe;
187 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
188 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x001f_ffff;
189}
190#[doc = "`reset()` method sets DMA_INT_CLR to value 0"]
191impl crate::Resettable for DMA_INT_CLR_SPEC {
192 const RESET_VALUE: u32 = 0;
193}