esp32p4/spi1/
flash_waiti_ctrl.rs

1#[doc = "Register `FLASH_WAITI_CTRL` reader"]
2pub type R = crate::R<FLASH_WAITI_CTRL_SPEC>;
3#[doc = "Register `FLASH_WAITI_CTRL` writer"]
4pub type W = crate::W<FLASH_WAITI_CTRL_SPEC>;
5#[doc = "Field `WAITI_EN` reader - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."]
6pub type WAITI_EN_R = crate::BitReader;
7#[doc = "Field `WAITI_EN` writer - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."]
8pub type WAITI_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `WAITI_DUMMY` reader - The dummy phase enable when wait flash idle (RDSR)"]
10pub type WAITI_DUMMY_R = crate::BitReader;
11#[doc = "Field `WAITI_DUMMY` writer - The dummy phase enable when wait flash idle (RDSR)"]
12pub type WAITI_DUMMY_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `WAITI_ADDR_EN` reader - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."]
14pub type WAITI_ADDR_EN_R = crate::BitReader;
15#[doc = "Field `WAITI_ADDR_EN` writer - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."]
16pub type WAITI_ADDR_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `WAITI_ADDR_CYCLELEN` reader - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."]
18pub type WAITI_ADDR_CYCLELEN_R = crate::FieldReader;
19#[doc = "Field `WAITI_ADDR_CYCLELEN` writer - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."]
20pub type WAITI_ADDR_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
21#[doc = "Field `WAITI_CMD_2B` reader - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."]
22pub type WAITI_CMD_2B_R = crate::BitReader;
23#[doc = "Field `WAITI_CMD_2B` writer - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."]
24pub type WAITI_CMD_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `WAITI_DUMMY_CYCLELEN` reader - The dummy cycle length when wait flash idle(RDSR)."]
26pub type WAITI_DUMMY_CYCLELEN_R = crate::FieldReader;
27#[doc = "Field `WAITI_DUMMY_CYCLELEN` writer - The dummy cycle length when wait flash idle(RDSR)."]
28pub type WAITI_DUMMY_CYCLELEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
29#[doc = "Field `WAITI_CMD` reader - The command value to wait flash idle(RDSR)."]
30pub type WAITI_CMD_R = crate::FieldReader<u16>;
31#[doc = "Field `WAITI_CMD` writer - The command value to wait flash idle(RDSR)."]
32pub type WAITI_CMD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
33impl R {
34    #[doc = "Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."]
35    #[inline(always)]
36    pub fn waiti_en(&self) -> WAITI_EN_R {
37        WAITI_EN_R::new((self.bits & 1) != 0)
38    }
39    #[doc = "Bit 1 - The dummy phase enable when wait flash idle (RDSR)"]
40    #[inline(always)]
41    pub fn waiti_dummy(&self) -> WAITI_DUMMY_R {
42        WAITI_DUMMY_R::new(((self.bits >> 1) & 1) != 0)
43    }
44    #[doc = "Bit 2 - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."]
45    #[inline(always)]
46    pub fn waiti_addr_en(&self) -> WAITI_ADDR_EN_R {
47        WAITI_ADDR_EN_R::new(((self.bits >> 2) & 1) != 0)
48    }
49    #[doc = "Bits 3:4 - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."]
50    #[inline(always)]
51    pub fn waiti_addr_cyclelen(&self) -> WAITI_ADDR_CYCLELEN_R {
52        WAITI_ADDR_CYCLELEN_R::new(((self.bits >> 3) & 3) as u8)
53    }
54    #[doc = "Bit 9 - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."]
55    #[inline(always)]
56    pub fn waiti_cmd_2b(&self) -> WAITI_CMD_2B_R {
57        WAITI_CMD_2B_R::new(((self.bits >> 9) & 1) != 0)
58    }
59    #[doc = "Bits 10:15 - The dummy cycle length when wait flash idle(RDSR)."]
60    #[inline(always)]
61    pub fn waiti_dummy_cyclelen(&self) -> WAITI_DUMMY_CYCLELEN_R {
62        WAITI_DUMMY_CYCLELEN_R::new(((self.bits >> 10) & 0x3f) as u8)
63    }
64    #[doc = "Bits 16:31 - The command value to wait flash idle(RDSR)."]
65    #[inline(always)]
66    pub fn waiti_cmd(&self) -> WAITI_CMD_R {
67        WAITI_CMD_R::new(((self.bits >> 16) & 0xffff) as u16)
68    }
69}
70#[cfg(feature = "impl-register-debug")]
71impl core::fmt::Debug for R {
72    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
73        f.debug_struct("FLASH_WAITI_CTRL")
74            .field("waiti_en", &format_args!("{}", self.waiti_en().bit()))
75            .field("waiti_dummy", &format_args!("{}", self.waiti_dummy().bit()))
76            .field(
77                "waiti_addr_en",
78                &format_args!("{}", self.waiti_addr_en().bit()),
79            )
80            .field(
81                "waiti_addr_cyclelen",
82                &format_args!("{}", self.waiti_addr_cyclelen().bits()),
83            )
84            .field(
85                "waiti_cmd_2b",
86                &format_args!("{}", self.waiti_cmd_2b().bit()),
87            )
88            .field(
89                "waiti_dummy_cyclelen",
90                &format_args!("{}", self.waiti_dummy_cyclelen().bits()),
91            )
92            .field("waiti_cmd", &format_args!("{}", self.waiti_cmd().bits()))
93            .finish()
94    }
95}
96#[cfg(feature = "impl-register-debug")]
97impl core::fmt::Debug for crate::generic::Reg<FLASH_WAITI_CTRL_SPEC> {
98    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
99        core::fmt::Debug::fmt(&self.read(), f)
100    }
101}
102impl W {
103    #[doc = "Bit 0 - 1: The hardware will wait idle after SE/PP/WRSR automatically, and hardware auto Suspend/Resume can be enabled. 0: The functions of hardware wait idle and auto Suspend/Resume are not supported."]
104    #[inline(always)]
105    #[must_use]
106    pub fn waiti_en(&mut self) -> WAITI_EN_W<FLASH_WAITI_CTRL_SPEC> {
107        WAITI_EN_W::new(self, 0)
108    }
109    #[doc = "Bit 1 - The dummy phase enable when wait flash idle (RDSR)"]
110    #[inline(always)]
111    #[must_use]
112    pub fn waiti_dummy(&mut self) -> WAITI_DUMMY_W<FLASH_WAITI_CTRL_SPEC> {
113        WAITI_DUMMY_W::new(self, 1)
114    }
115    #[doc = "Bit 2 - 1: Output address 0 in RDSR or read SUS command transfer. 0: Do not send out address in RDSR or read SUS command transfer."]
116    #[inline(always)]
117    #[must_use]
118    pub fn waiti_addr_en(&mut self) -> WAITI_ADDR_EN_W<FLASH_WAITI_CTRL_SPEC> {
119        WAITI_ADDR_EN_W::new(self, 2)
120    }
121    #[doc = "Bits 3:4 - When SPI_MEM_WAITI_ADDR_EN is set, the cycle length of sent out address is (SPI_MEM_WAITI_ADDR_CYCLELEN\\[1:0\\] + 1) SPI bus clock cycles. It is not active when SPI_MEM_WAITI_ADDR_EN is cleared."]
122    #[inline(always)]
123    #[must_use]
124    pub fn waiti_addr_cyclelen(&mut self) -> WAITI_ADDR_CYCLELEN_W<FLASH_WAITI_CTRL_SPEC> {
125        WAITI_ADDR_CYCLELEN_W::new(self, 3)
126    }
127    #[doc = "Bit 9 - 1:The wait idle command bit length is 16. 0: The wait idle command bit length is 8."]
128    #[inline(always)]
129    #[must_use]
130    pub fn waiti_cmd_2b(&mut self) -> WAITI_CMD_2B_W<FLASH_WAITI_CTRL_SPEC> {
131        WAITI_CMD_2B_W::new(self, 9)
132    }
133    #[doc = "Bits 10:15 - The dummy cycle length when wait flash idle(RDSR)."]
134    #[inline(always)]
135    #[must_use]
136    pub fn waiti_dummy_cyclelen(&mut self) -> WAITI_DUMMY_CYCLELEN_W<FLASH_WAITI_CTRL_SPEC> {
137        WAITI_DUMMY_CYCLELEN_W::new(self, 10)
138    }
139    #[doc = "Bits 16:31 - The command value to wait flash idle(RDSR)."]
140    #[inline(always)]
141    #[must_use]
142    pub fn waiti_cmd(&mut self) -> WAITI_CMD_W<FLASH_WAITI_CTRL_SPEC> {
143        WAITI_CMD_W::new(self, 16)
144    }
145}
146#[doc = "SPI1 wait idle control register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`flash_waiti_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`flash_waiti_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
147pub struct FLASH_WAITI_CTRL_SPEC;
148impl crate::RegisterSpec for FLASH_WAITI_CTRL_SPEC {
149    type Ux = u32;
150}
151#[doc = "`read()` method returns [`flash_waiti_ctrl::R`](R) reader structure"]
152impl crate::Readable for FLASH_WAITI_CTRL_SPEC {}
153#[doc = "`write(|w| ..)` method takes [`flash_waiti_ctrl::W`](W) writer structure"]
154impl crate::Writable for FLASH_WAITI_CTRL_SPEC {
155    type Safety = crate::Unsafe;
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
158}
159#[doc = "`reset()` method sets FLASH_WAITI_CTRL to value 0x0005_0001"]
160impl crate::Resettable for FLASH_WAITI_CTRL_SPEC {
161    const RESET_VALUE: u32 = 0x0005_0001;
162}
esp32p4/spi1/flash_waiti_ctrl.rs

esp32p4/spi1/
flash_waiti_ctrl.rs
