1#[doc = "Register `CTRL` reader"]
2pub type R = crate::R<CTRL_SPEC>;
3#[doc = "Register `CTRL` writer"]
4pub type W = crate::W<CTRL_SPEC>;
5#[doc = "Field `FDUMMY_RIN` reader - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
6pub type FDUMMY_RIN_R = crate::BitReader;
7#[doc = "Field `FDUMMY_RIN` writer - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
8pub type FDUMMY_RIN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `FDUMMY_WOUT` reader - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
10pub type FDUMMY_WOUT_R = crate::BitReader;
11#[doc = "Field `FDUMMY_WOUT` writer - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
12pub type FDUMMY_WOUT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `FDOUT_OCT` reader - Apply 8 signals during write-data phase 1:enable 0: disable"]
14pub type FDOUT_OCT_R = crate::BitReader;
15#[doc = "Field `FDOUT_OCT` writer - Apply 8 signals during write-data phase 1:enable 0: disable"]
16pub type FDOUT_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FDIN_OCT` reader - Apply 8 signals during read-data phase 1:enable 0: disable"]
18pub type FDIN_OCT_R = crate::BitReader;
19#[doc = "Field `FDIN_OCT` writer - Apply 8 signals during read-data phase 1:enable 0: disable"]
20pub type FDIN_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FADDR_OCT` reader - Apply 8 signals during address phase 1:enable 0: disable"]
22pub type FADDR_OCT_R = crate::BitReader;
23#[doc = "Field `FADDR_OCT` writer - Apply 8 signals during address phase 1:enable 0: disable"]
24pub type FADDR_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FCMD_QUAD` reader - Apply 4 signals during command phase 1:enable 0: disable"]
26pub type FCMD_QUAD_R = crate::BitReader;
27#[doc = "Field `FCMD_QUAD` writer - Apply 4 signals during command phase 1:enable 0: disable"]
28pub type FCMD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FCMD_OCT` reader - Apply 8 signals during command phase 1:enable 0: disable"]
30pub type FCMD_OCT_R = crate::BitReader;
31#[doc = "Field `FCMD_OCT` writer - Apply 8 signals during command phase 1:enable 0: disable"]
32pub type FCMD_OCT_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FCS_CRC_EN` reader - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
34pub type FCS_CRC_EN_R = crate::BitReader;
35#[doc = "Field `FCS_CRC_EN` writer - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
36pub type FCS_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `TX_CRC_EN` reader - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
38pub type TX_CRC_EN_R = crate::BitReader;
39#[doc = "Field `TX_CRC_EN` writer - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
40pub type TX_CRC_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `FASTRD_MODE` reader - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
42pub type FASTRD_MODE_R = crate::BitReader;
43#[doc = "Field `FASTRD_MODE` writer - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
44pub type FASTRD_MODE_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `FREAD_DUAL` reader - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
46pub type FREAD_DUAL_R = crate::BitReader;
47#[doc = "Field `FREAD_DUAL` writer - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
48pub type FREAD_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `RESANDRES` reader - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
50pub type RESANDRES_R = crate::BitReader;
51#[doc = "Field `RESANDRES` writer - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
52pub type RESANDRES_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `Q_POL` reader - The bit is used to set MISO line polarity, 1: high 0, low"]
54pub type Q_POL_R = crate::BitReader;
55#[doc = "Field `Q_POL` writer - The bit is used to set MISO line polarity, 1: high 0, low"]
56pub type Q_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `D_POL` reader - The bit is used to set MOSI line polarity, 1: high 0, low"]
58pub type D_POL_R = crate::BitReader;
59#[doc = "Field `D_POL` writer - The bit is used to set MOSI line polarity, 1: high 0, low"]
60pub type D_POL_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `FREAD_QUAD` reader - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
62pub type FREAD_QUAD_R = crate::BitReader;
63#[doc = "Field `FREAD_QUAD` writer - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
64pub type FREAD_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `WP` reader - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
66pub type WP_R = crate::BitReader;
67#[doc = "Field `WP` writer - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
68pub type WP_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `WRSR_2B` reader - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
70pub type WRSR_2B_R = crate::BitReader;
71#[doc = "Field `WRSR_2B` writer - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
72pub type WRSR_2B_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `FREAD_DIO` reader - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
74pub type FREAD_DIO_R = crate::BitReader;
75#[doc = "Field `FREAD_DIO` writer - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
76pub type FREAD_DIO_W<'a, REG> = crate::BitWriter<'a, REG>;
77#[doc = "Field `FREAD_QIO` reader - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
78pub type FREAD_QIO_R = crate::BitReader;
79#[doc = "Field `FREAD_QIO` writer - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
80pub type FREAD_QIO_W<'a, REG> = crate::BitWriter<'a, REG>;
81impl R {
82 #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
83 #[inline(always)]
84 pub fn fdummy_rin(&self) -> FDUMMY_RIN_R {
85 FDUMMY_RIN_R::new(((self.bits >> 2) & 1) != 0)
86 }
87 #[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
88 #[inline(always)]
89 pub fn fdummy_wout(&self) -> FDUMMY_WOUT_R {
90 FDUMMY_WOUT_R::new(((self.bits >> 3) & 1) != 0)
91 }
92 #[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"]
93 #[inline(always)]
94 pub fn fdout_oct(&self) -> FDOUT_OCT_R {
95 FDOUT_OCT_R::new(((self.bits >> 4) & 1) != 0)
96 }
97 #[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"]
98 #[inline(always)]
99 pub fn fdin_oct(&self) -> FDIN_OCT_R {
100 FDIN_OCT_R::new(((self.bits >> 5) & 1) != 0)
101 }
102 #[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"]
103 #[inline(always)]
104 pub fn faddr_oct(&self) -> FADDR_OCT_R {
105 FADDR_OCT_R::new(((self.bits >> 6) & 1) != 0)
106 }
107 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
108 #[inline(always)]
109 pub fn fcmd_quad(&self) -> FCMD_QUAD_R {
110 FCMD_QUAD_R::new(((self.bits >> 8) & 1) != 0)
111 }
112 #[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"]
113 #[inline(always)]
114 pub fn fcmd_oct(&self) -> FCMD_OCT_R {
115 FCMD_OCT_R::new(((self.bits >> 9) & 1) != 0)
116 }
117 #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
118 #[inline(always)]
119 pub fn fcs_crc_en(&self) -> FCS_CRC_EN_R {
120 FCS_CRC_EN_R::new(((self.bits >> 10) & 1) != 0)
121 }
122 #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
123 #[inline(always)]
124 pub fn tx_crc_en(&self) -> TX_CRC_EN_R {
125 TX_CRC_EN_R::new(((self.bits >> 11) & 1) != 0)
126 }
127 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
128 #[inline(always)]
129 pub fn fastrd_mode(&self) -> FASTRD_MODE_R {
130 FASTRD_MODE_R::new(((self.bits >> 13) & 1) != 0)
131 }
132 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
133 #[inline(always)]
134 pub fn fread_dual(&self) -> FREAD_DUAL_R {
135 FREAD_DUAL_R::new(((self.bits >> 14) & 1) != 0)
136 }
137 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
138 #[inline(always)]
139 pub fn resandres(&self) -> RESANDRES_R {
140 RESANDRES_R::new(((self.bits >> 15) & 1) != 0)
141 }
142 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
143 #[inline(always)]
144 pub fn q_pol(&self) -> Q_POL_R {
145 Q_POL_R::new(((self.bits >> 18) & 1) != 0)
146 }
147 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
148 #[inline(always)]
149 pub fn d_pol(&self) -> D_POL_R {
150 D_POL_R::new(((self.bits >> 19) & 1) != 0)
151 }
152 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
153 #[inline(always)]
154 pub fn fread_quad(&self) -> FREAD_QUAD_R {
155 FREAD_QUAD_R::new(((self.bits >> 20) & 1) != 0)
156 }
157 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
158 #[inline(always)]
159 pub fn wp(&self) -> WP_R {
160 WP_R::new(((self.bits >> 21) & 1) != 0)
161 }
162 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
163 #[inline(always)]
164 pub fn wrsr_2b(&self) -> WRSR_2B_R {
165 WRSR_2B_R::new(((self.bits >> 22) & 1) != 0)
166 }
167 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
168 #[inline(always)]
169 pub fn fread_dio(&self) -> FREAD_DIO_R {
170 FREAD_DIO_R::new(((self.bits >> 23) & 1) != 0)
171 }
172 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
173 #[inline(always)]
174 pub fn fread_qio(&self) -> FREAD_QIO_R {
175 FREAD_QIO_R::new(((self.bits >> 24) & 1) != 0)
176 }
177}
178#[cfg(feature = "impl-register-debug")]
179impl core::fmt::Debug for R {
180 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
181 f.debug_struct("CTRL")
182 .field("fdummy_rin", &format_args!("{}", self.fdummy_rin().bit()))
183 .field("fdummy_wout", &format_args!("{}", self.fdummy_wout().bit()))
184 .field("fdout_oct", &format_args!("{}", self.fdout_oct().bit()))
185 .field("fdin_oct", &format_args!("{}", self.fdin_oct().bit()))
186 .field("faddr_oct", &format_args!("{}", self.faddr_oct().bit()))
187 .field("fcmd_quad", &format_args!("{}", self.fcmd_quad().bit()))
188 .field("fcmd_oct", &format_args!("{}", self.fcmd_oct().bit()))
189 .field("fcs_crc_en", &format_args!("{}", self.fcs_crc_en().bit()))
190 .field("tx_crc_en", &format_args!("{}", self.tx_crc_en().bit()))
191 .field("fastrd_mode", &format_args!("{}", self.fastrd_mode().bit()))
192 .field("fread_dual", &format_args!("{}", self.fread_dual().bit()))
193 .field("resandres", &format_args!("{}", self.resandres().bit()))
194 .field("q_pol", &format_args!("{}", self.q_pol().bit()))
195 .field("d_pol", &format_args!("{}", self.d_pol().bit()))
196 .field("fread_quad", &format_args!("{}", self.fread_quad().bit()))
197 .field("wp", &format_args!("{}", self.wp().bit()))
198 .field("wrsr_2b", &format_args!("{}", self.wrsr_2b().bit()))
199 .field("fread_dio", &format_args!("{}", self.fread_dio().bit()))
200 .field("fread_qio", &format_args!("{}", self.fread_qio().bit()))
201 .finish()
202 }
203}
204#[cfg(feature = "impl-register-debug")]
205impl core::fmt::Debug for crate::generic::Reg<CTRL_SPEC> {
206 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
207 core::fmt::Debug::fmt(&self.read(), f)
208 }
209}
210impl W {
211 #[doc = "Bit 2 - In the dummy phase of a MSPI read data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
212 #[inline(always)]
213 #[must_use]
214 pub fn fdummy_rin(&mut self) -> FDUMMY_RIN_W<CTRL_SPEC> {
215 FDUMMY_RIN_W::new(self, 2)
216 }
217 #[doc = "Bit 3 - In the dummy phase of a MSPI write data transfer when accesses to flash, the signal level of SPI bus is output by the MSPI controller."]
218 #[inline(always)]
219 #[must_use]
220 pub fn fdummy_wout(&mut self) -> FDUMMY_WOUT_W<CTRL_SPEC> {
221 FDUMMY_WOUT_W::new(self, 3)
222 }
223 #[doc = "Bit 4 - Apply 8 signals during write-data phase 1:enable 0: disable"]
224 #[inline(always)]
225 #[must_use]
226 pub fn fdout_oct(&mut self) -> FDOUT_OCT_W<CTRL_SPEC> {
227 FDOUT_OCT_W::new(self, 4)
228 }
229 #[doc = "Bit 5 - Apply 8 signals during read-data phase 1:enable 0: disable"]
230 #[inline(always)]
231 #[must_use]
232 pub fn fdin_oct(&mut self) -> FDIN_OCT_W<CTRL_SPEC> {
233 FDIN_OCT_W::new(self, 5)
234 }
235 #[doc = "Bit 6 - Apply 8 signals during address phase 1:enable 0: disable"]
236 #[inline(always)]
237 #[must_use]
238 pub fn faddr_oct(&mut self) -> FADDR_OCT_W<CTRL_SPEC> {
239 FADDR_OCT_W::new(self, 6)
240 }
241 #[doc = "Bit 8 - Apply 4 signals during command phase 1:enable 0: disable"]
242 #[inline(always)]
243 #[must_use]
244 pub fn fcmd_quad(&mut self) -> FCMD_QUAD_W<CTRL_SPEC> {
245 FCMD_QUAD_W::new(self, 8)
246 }
247 #[doc = "Bit 9 - Apply 8 signals during command phase 1:enable 0: disable"]
248 #[inline(always)]
249 #[must_use]
250 pub fn fcmd_oct(&mut self) -> FCMD_OCT_W<CTRL_SPEC> {
251 FCMD_OCT_W::new(self, 9)
252 }
253 #[doc = "Bit 10 - For SPI1, initialize crc32 module before writing encrypted data to flash. Active low."]
254 #[inline(always)]
255 #[must_use]
256 pub fn fcs_crc_en(&mut self) -> FCS_CRC_EN_W<CTRL_SPEC> {
257 FCS_CRC_EN_W::new(self, 10)
258 }
259 #[doc = "Bit 11 - For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable"]
260 #[inline(always)]
261 #[must_use]
262 pub fn tx_crc_en(&mut self) -> TX_CRC_EN_W<CTRL_SPEC> {
263 TX_CRC_EN_W::new(self, 11)
264 }
265 #[doc = "Bit 13 - This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable."]
266 #[inline(always)]
267 #[must_use]
268 pub fn fastrd_mode(&mut self) -> FASTRD_MODE_W<CTRL_SPEC> {
269 FASTRD_MODE_W::new(self, 13)
270 }
271 #[doc = "Bit 14 - In the read operations, read-data phase apply 2 signals. 1: enable 0: disable."]
272 #[inline(always)]
273 #[must_use]
274 pub fn fread_dual(&mut self) -> FREAD_DUAL_W<CTRL_SPEC> {
275 FREAD_DUAL_W::new(self, 14)
276 }
277 #[doc = "Bit 15 - The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable."]
278 #[inline(always)]
279 #[must_use]
280 pub fn resandres(&mut self) -> RESANDRES_W<CTRL_SPEC> {
281 RESANDRES_W::new(self, 15)
282 }
283 #[doc = "Bit 18 - The bit is used to set MISO line polarity, 1: high 0, low"]
284 #[inline(always)]
285 #[must_use]
286 pub fn q_pol(&mut self) -> Q_POL_W<CTRL_SPEC> {
287 Q_POL_W::new(self, 18)
288 }
289 #[doc = "Bit 19 - The bit is used to set MOSI line polarity, 1: high 0, low"]
290 #[inline(always)]
291 #[must_use]
292 pub fn d_pol(&mut self) -> D_POL_W<CTRL_SPEC> {
293 D_POL_W::new(self, 19)
294 }
295 #[doc = "Bit 20 - In the read operations read-data phase apply 4 signals. 1: enable 0: disable."]
296 #[inline(always)]
297 #[must_use]
298 pub fn fread_quad(&mut self) -> FREAD_QUAD_W<CTRL_SPEC> {
299 FREAD_QUAD_W::new(self, 20)
300 }
301 #[doc = "Bit 21 - Write protect signal output when SPI is idle. 1: output high, 0: output low."]
302 #[inline(always)]
303 #[must_use]
304 pub fn wp(&mut self) -> WP_W<CTRL_SPEC> {
305 WP_W::new(self, 21)
306 }
307 #[doc = "Bit 22 - two bytes data will be written to status register when it is set. 1: enable 0: disable."]
308 #[inline(always)]
309 #[must_use]
310 pub fn wrsr_2b(&mut self) -> WRSR_2B_W<CTRL_SPEC> {
311 WRSR_2B_W::new(self, 22)
312 }
313 #[doc = "Bit 23 - In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable."]
314 #[inline(always)]
315 #[must_use]
316 pub fn fread_dio(&mut self) -> FREAD_DIO_W<CTRL_SPEC> {
317 FREAD_DIO_W::new(self, 23)
318 }
319 #[doc = "Bit 24 - In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable."]
320 #[inline(always)]
321 #[must_use]
322 pub fn fread_qio(&mut self) -> FREAD_QIO_W<CTRL_SPEC> {
323 FREAD_QIO_W::new(self, 24)
324 }
325}
326#[doc = "SPI1 control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
327pub struct CTRL_SPEC;
328impl crate::RegisterSpec for CTRL_SPEC {
329 type Ux = u32;
330}
331#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
332impl crate::Readable for CTRL_SPEC {}
333#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
334impl crate::Writable for CTRL_SPEC {
335 type Safety = crate::Unsafe;
336 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
337 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
338}
339#[doc = "`reset()` method sets CTRL to value 0x002c_a00c"]
340impl crate::Resettable for CTRL_SPEC {
341 const RESET_VALUE: u32 = 0x002c_a00c;
342}