1#[doc = "Register `CACHE_FCTRL` reader"]
2pub type R = crate::R<CACHE_FCTRL_SPEC>;
3#[doc = "Register `CACHE_FCTRL` writer"]
4pub type W = crate::W<CACHE_FCTRL_SPEC>;
5#[doc = "Field `AXI_REQ_EN` reader - For SPI0, AXI master access enable, 1: enable, 0:disable."]
6pub type AXI_REQ_EN_R = crate::BitReader;
7#[doc = "Field `AXI_REQ_EN` writer - For SPI0, AXI master access enable, 1: enable, 0:disable."]
8pub type AXI_REQ_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `CACHE_USR_ADDR_4BYTE` reader - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
10pub type CACHE_USR_ADDR_4BYTE_R = crate::BitReader;
11#[doc = "Field `CACHE_USR_ADDR_4BYTE` writer - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
12pub type CACHE_USR_ADDR_4BYTE_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `CACHE_FLASH_USR_CMD` reader - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
14pub type CACHE_FLASH_USR_CMD_R = crate::BitReader;
15#[doc = "Field `CACHE_FLASH_USR_CMD` writer - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
16pub type CACHE_FLASH_USR_CMD_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `FDIN_DUAL` reader - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
18pub type FDIN_DUAL_R = crate::BitReader;
19#[doc = "Field `FDIN_DUAL` writer - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
20pub type FDIN_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `FDOUT_DUAL` reader - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
22pub type FDOUT_DUAL_R = crate::BitReader;
23#[doc = "Field `FDOUT_DUAL` writer - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
24pub type FDOUT_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `FADDR_DUAL` reader - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
26pub type FADDR_DUAL_R = crate::BitReader;
27#[doc = "Field `FADDR_DUAL` writer - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
28pub type FADDR_DUAL_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `FDIN_QUAD` reader - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
30pub type FDIN_QUAD_R = crate::BitReader;
31#[doc = "Field `FDIN_QUAD` writer - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
32pub type FDIN_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `FDOUT_QUAD` reader - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
34pub type FDOUT_QUAD_R = crate::BitReader;
35#[doc = "Field `FDOUT_QUAD` writer - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
36pub type FDOUT_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `FADDR_QUAD` reader - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
38pub type FADDR_QUAD_R = crate::BitReader;
39#[doc = "Field `FADDR_QUAD` writer - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
40pub type FADDR_QUAD_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `SPI_SAME_AW_AR_ADDR_CHK_EN` reader - Set this bit to check AXI read/write the same address region."]
42pub type SPI_SAME_AW_AR_ADDR_CHK_EN_R = crate::BitReader;
43#[doc = "Field `SPI_SAME_AW_AR_ADDR_CHK_EN` writer - Set this bit to check AXI read/write the same address region."]
44pub type SPI_SAME_AW_AR_ADDR_CHK_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `SPI_CLOSE_AXI_INF_EN` reader - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."]
46pub type SPI_CLOSE_AXI_INF_EN_R = crate::BitReader;
47#[doc = "Field `SPI_CLOSE_AXI_INF_EN` writer - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."]
48pub type SPI_CLOSE_AXI_INF_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
49impl R {
50 #[doc = "Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable."]
51 #[inline(always)]
52 pub fn axi_req_en(&self) -> AXI_REQ_EN_R {
53 AXI_REQ_EN_R::new((self.bits & 1) != 0)
54 }
55 #[doc = "Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
56 #[inline(always)]
57 pub fn cache_usr_addr_4byte(&self) -> CACHE_USR_ADDR_4BYTE_R {
58 CACHE_USR_ADDR_4BYTE_R::new(((self.bits >> 1) & 1) != 0)
59 }
60 #[doc = "Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
61 #[inline(always)]
62 pub fn cache_flash_usr_cmd(&self) -> CACHE_FLASH_USR_CMD_R {
63 CACHE_FLASH_USR_CMD_R::new(((self.bits >> 2) & 1) != 0)
64 }
65 #[doc = "Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
66 #[inline(always)]
67 pub fn fdin_dual(&self) -> FDIN_DUAL_R {
68 FDIN_DUAL_R::new(((self.bits >> 3) & 1) != 0)
69 }
70 #[doc = "Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
71 #[inline(always)]
72 pub fn fdout_dual(&self) -> FDOUT_DUAL_R {
73 FDOUT_DUAL_R::new(((self.bits >> 4) & 1) != 0)
74 }
75 #[doc = "Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
76 #[inline(always)]
77 pub fn faddr_dual(&self) -> FADDR_DUAL_R {
78 FADDR_DUAL_R::new(((self.bits >> 5) & 1) != 0)
79 }
80 #[doc = "Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
81 #[inline(always)]
82 pub fn fdin_quad(&self) -> FDIN_QUAD_R {
83 FDIN_QUAD_R::new(((self.bits >> 6) & 1) != 0)
84 }
85 #[doc = "Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
86 #[inline(always)]
87 pub fn fdout_quad(&self) -> FDOUT_QUAD_R {
88 FDOUT_QUAD_R::new(((self.bits >> 7) & 1) != 0)
89 }
90 #[doc = "Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
91 #[inline(always)]
92 pub fn faddr_quad(&self) -> FADDR_QUAD_R {
93 FADDR_QUAD_R::new(((self.bits >> 8) & 1) != 0)
94 }
95 #[doc = "Bit 30 - Set this bit to check AXI read/write the same address region."]
96 #[inline(always)]
97 pub fn spi_same_aw_ar_addr_chk_en(&self) -> SPI_SAME_AW_AR_ADDR_CHK_EN_R {
98 SPI_SAME_AW_AR_ADDR_CHK_EN_R::new(((self.bits >> 30) & 1) != 0)
99 }
100 #[doc = "Bit 31 - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."]
101 #[inline(always)]
102 pub fn spi_close_axi_inf_en(&self) -> SPI_CLOSE_AXI_INF_EN_R {
103 SPI_CLOSE_AXI_INF_EN_R::new(((self.bits >> 31) & 1) != 0)
104 }
105}
106#[cfg(feature = "impl-register-debug")]
107impl core::fmt::Debug for R {
108 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
109 f.debug_struct("CACHE_FCTRL")
110 .field("axi_req_en", &format_args!("{}", self.axi_req_en().bit()))
111 .field(
112 "cache_usr_addr_4byte",
113 &format_args!("{}", self.cache_usr_addr_4byte().bit()),
114 )
115 .field(
116 "cache_flash_usr_cmd",
117 &format_args!("{}", self.cache_flash_usr_cmd().bit()),
118 )
119 .field("fdin_dual", &format_args!("{}", self.fdin_dual().bit()))
120 .field("fdout_dual", &format_args!("{}", self.fdout_dual().bit()))
121 .field("faddr_dual", &format_args!("{}", self.faddr_dual().bit()))
122 .field("fdin_quad", &format_args!("{}", self.fdin_quad().bit()))
123 .field("fdout_quad", &format_args!("{}", self.fdout_quad().bit()))
124 .field("faddr_quad", &format_args!("{}", self.faddr_quad().bit()))
125 .field(
126 "spi_same_aw_ar_addr_chk_en",
127 &format_args!("{}", self.spi_same_aw_ar_addr_chk_en().bit()),
128 )
129 .field(
130 "spi_close_axi_inf_en",
131 &format_args!("{}", self.spi_close_axi_inf_en().bit()),
132 )
133 .finish()
134 }
135}
136#[cfg(feature = "impl-register-debug")]
137impl core::fmt::Debug for crate::generic::Reg<CACHE_FCTRL_SPEC> {
138 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
139 core::fmt::Debug::fmt(&self.read(), f)
140 }
141}
142impl W {
143 #[doc = "Bit 0 - For SPI0, AXI master access enable, 1: enable, 0:disable."]
144 #[inline(always)]
145 #[must_use]
146 pub fn axi_req_en(&mut self) -> AXI_REQ_EN_W<CACHE_FCTRL_SPEC> {
147 AXI_REQ_EN_W::new(self, 0)
148 }
149 #[doc = "Bit 1 - For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable."]
150 #[inline(always)]
151 #[must_use]
152 pub fn cache_usr_addr_4byte(&mut self) -> CACHE_USR_ADDR_4BYTE_W<CACHE_FCTRL_SPEC> {
153 CACHE_USR_ADDR_4BYTE_W::new(self, 1)
154 }
155 #[doc = "Bit 2 - For SPI0, cache read flash for user define command, 1: enable, 0:disable."]
156 #[inline(always)]
157 #[must_use]
158 pub fn cache_flash_usr_cmd(&mut self) -> CACHE_FLASH_USR_CMD_W<CACHE_FCTRL_SPEC> {
159 CACHE_FLASH_USR_CMD_W::new(self, 2)
160 }
161 #[doc = "Bit 3 - For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
162 #[inline(always)]
163 #[must_use]
164 pub fn fdin_dual(&mut self) -> FDIN_DUAL_W<CACHE_FCTRL_SPEC> {
165 FDIN_DUAL_W::new(self, 3)
166 }
167 #[doc = "Bit 4 - For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
168 #[inline(always)]
169 #[must_use]
170 pub fn fdout_dual(&mut self) -> FDOUT_DUAL_W<CACHE_FCTRL_SPEC> {
171 FDOUT_DUAL_W::new(self, 4)
172 }
173 #[doc = "Bit 5 - For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio."]
174 #[inline(always)]
175 #[must_use]
176 pub fn faddr_dual(&mut self) -> FADDR_DUAL_W<CACHE_FCTRL_SPEC> {
177 FADDR_DUAL_W::new(self, 5)
178 }
179 #[doc = "Bit 6 - For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
180 #[inline(always)]
181 #[must_use]
182 pub fn fdin_quad(&mut self) -> FDIN_QUAD_W<CACHE_FCTRL_SPEC> {
183 FDIN_QUAD_W::new(self, 6)
184 }
185 #[doc = "Bit 7 - For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
186 #[inline(always)]
187 #[must_use]
188 pub fn fdout_quad(&mut self) -> FDOUT_QUAD_W<CACHE_FCTRL_SPEC> {
189 FDOUT_QUAD_W::new(self, 7)
190 }
191 #[doc = "Bit 8 - For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio."]
192 #[inline(always)]
193 #[must_use]
194 pub fn faddr_quad(&mut self) -> FADDR_QUAD_W<CACHE_FCTRL_SPEC> {
195 FADDR_QUAD_W::new(self, 8)
196 }
197 #[doc = "Bit 30 - Set this bit to check AXI read/write the same address region."]
198 #[inline(always)]
199 #[must_use]
200 pub fn spi_same_aw_ar_addr_chk_en(&mut self) -> SPI_SAME_AW_AR_ADDR_CHK_EN_W<CACHE_FCTRL_SPEC> {
201 SPI_SAME_AW_AR_ADDR_CHK_EN_W::new(self, 30)
202 }
203 #[doc = "Bit 31 - Set this bit to close AXI read/write transfer to MSPI, which means that only SLV_ERR will be replied to BRESP/RRESP."]
204 #[inline(always)]
205 #[must_use]
206 pub fn spi_close_axi_inf_en(&mut self) -> SPI_CLOSE_AXI_INF_EN_W<CACHE_FCTRL_SPEC> {
207 SPI_CLOSE_AXI_INF_EN_W::new(self, 31)
208 }
209}
210#[doc = "SPI0 bit mode control register.\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`cache_fctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cache_fctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
211pub struct CACHE_FCTRL_SPEC;
212impl crate::RegisterSpec for CACHE_FCTRL_SPEC {
213 type Ux = u32;
214}
215#[doc = "`read()` method returns [`cache_fctrl::R`](R) reader structure"]
216impl crate::Readable for CACHE_FCTRL_SPEC {}
217#[doc = "`write(|w| ..)` method takes [`cache_fctrl::W`](W) writer structure"]
218impl crate::Writable for CACHE_FCTRL_SPEC {
219 type Safety = crate::Unsafe;
220 const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
221 const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
222}
223#[doc = "`reset()` method sets CACHE_FCTRL to value 0xc000_0000"]
224impl crate::Resettable for CACHE_FCTRL_SPEC {
225 const RESET_VALUE: u32 = 0xc000_0000;
226}