esp32p4/rmt/
int_clr.rs

1#[doc = "Register `INT_CLR` writer"]
2pub type W = crate::W<INT_CLR_SPEC>;
3#[doc = "Field `CH0_TX_END` writer - Set this bit to clear theCH0_TX_END_INT interrupt."]
4pub type CH0_TX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
5#[doc = "Field `CH1_TX_END` writer - Set this bit to clear theCH1_TX_END_INT interrupt."]
6pub type CH1_TX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
7#[doc = "Field `CH2_TX_END` writer - Set this bit to clear theCH2_TX_END_INT interrupt."]
8pub type CH2_TX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
9#[doc = "Field `CH3_TX_END` writer - Set this bit to clear theCH3_TX_END_INT interrupt."]
10pub type CH3_TX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
11#[doc = "Field `TX_CH0_ERR` writer - Set this bit to clear theCH0_ERR_INT interrupt."]
12pub type TX_CH0_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
13#[doc = "Field `TX_CH1_ERR` writer - Set this bit to clear theCH1_ERR_INT interrupt."]
14pub type TX_CH1_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
15#[doc = "Field `TX_CH2_ERR` writer - Set this bit to clear theCH2_ERR_INT interrupt."]
16pub type TX_CH2_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
17#[doc = "Field `TX_CH3_ERR` writer - Set this bit to clear theCH3_ERR_INT interrupt."]
18pub type TX_CH3_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
19#[doc = "Field `CH0_TX_THR_EVENT` writer - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."]
20pub type CH0_TX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
21#[doc = "Field `CH1_TX_THR_EVENT` writer - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."]
22pub type CH1_TX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
23#[doc = "Field `CH2_TX_THR_EVENT` writer - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt."]
24pub type CH2_TX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
25#[doc = "Field `CH3_TX_THR_EVENT` writer - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt."]
26pub type CH3_TX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
27#[doc = "Field `CH0_TX_LOOP` writer - Set this bit to clear theCH0_TX_LOOP_INT interrupt."]
28pub type CH0_TX_LOOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
29#[doc = "Field `CH1_TX_LOOP` writer - Set this bit to clear theCH1_TX_LOOP_INT interrupt."]
30pub type CH1_TX_LOOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
31#[doc = "Field `CH2_TX_LOOP` writer - Set this bit to clear theCH2_TX_LOOP_INT interrupt."]
32pub type CH2_TX_LOOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
33#[doc = "Field `CH3_TX_LOOP` writer - Set this bit to clear theCH3_TX_LOOP_INT interrupt."]
34pub type CH3_TX_LOOP_W<'a, REG> = crate::BitWriter1C<'a, REG>;
35#[doc = "Field `CH4_RX_END` writer - Set this bit to clear theCH4_RX_END_INT interrupt."]
36pub type CH4_RX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
37#[doc = "Field `CH5_RX_END` writer - Set this bit to clear theCH5_RX_END_INT interrupt."]
38pub type CH5_RX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
39#[doc = "Field `CH6_RX_END` writer - Set this bit to clear theCH6_RX_END_INT interrupt."]
40pub type CH6_RX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
41#[doc = "Field `CH7_RX_END` writer - Set this bit to clear theCH7_RX_END_INT interrupt."]
42pub type CH7_RX_END_W<'a, REG> = crate::BitWriter1C<'a, REG>;
43#[doc = "Field `RX_CH4_ERR` writer - Set this bit to clear theCH4_ERR_INT interrupt."]
44pub type RX_CH4_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
45#[doc = "Field `RX_CH5_ERR` writer - Set this bit to clear theCH5_ERR_INT interrupt."]
46pub type RX_CH5_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
47#[doc = "Field `RX_CH6_ERR` writer - Set this bit to clear theCH6_ERR_INT interrupt."]
48pub type RX_CH6_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
49#[doc = "Field `RX_CH7_ERR` writer - Set this bit to clear theCH7_ERR_INT interrupt."]
50pub type RX_CH7_ERR_W<'a, REG> = crate::BitWriter1C<'a, REG>;
51#[doc = "Field `CH4_RX_THR_EVENT` writer - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
52pub type CH4_RX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
53#[doc = "Field `CH5_RX_THR_EVENT` writer - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt."]
54pub type CH5_RX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
55#[doc = "Field `CH6_RX_THR_EVENT` writer - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt."]
56pub type CH6_RX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
57#[doc = "Field `CH7_RX_THR_EVENT` writer - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt."]
58pub type CH7_RX_THR_EVENT_W<'a, REG> = crate::BitWriter1C<'a, REG>;
59#[doc = "Field `TX_CH3_DMA_ACCESS_FAIL` writer - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."]
60pub type TX_CH3_DMA_ACCESS_FAIL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
61#[doc = "Field `RX_CH7_DMA_ACCESS_FAIL` writer - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."]
62pub type RX_CH7_DMA_ACCESS_FAIL_W<'a, REG> = crate::BitWriter1C<'a, REG>;
63#[cfg(feature = "impl-register-debug")]
64impl core::fmt::Debug for crate::generic::Reg<INT_CLR_SPEC> {
65    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
66        write!(f, "(not readable)")
67    }
68}
69impl W {
70    #[doc = "Bit 0 - Set this bit to clear theCH0_TX_END_INT interrupt."]
71    #[inline(always)]
72    #[must_use]
73    pub fn ch0_tx_end(&mut self) -> CH0_TX_END_W<INT_CLR_SPEC> {
74        CH0_TX_END_W::new(self, 0)
75    }
76    #[doc = "Bit 1 - Set this bit to clear theCH1_TX_END_INT interrupt."]
77    #[inline(always)]
78    #[must_use]
79    pub fn ch1_tx_end(&mut self) -> CH1_TX_END_W<INT_CLR_SPEC> {
80        CH1_TX_END_W::new(self, 1)
81    }
82    #[doc = "Bit 2 - Set this bit to clear theCH2_TX_END_INT interrupt."]
83    #[inline(always)]
84    #[must_use]
85    pub fn ch2_tx_end(&mut self) -> CH2_TX_END_W<INT_CLR_SPEC> {
86        CH2_TX_END_W::new(self, 2)
87    }
88    #[doc = "Bit 3 - Set this bit to clear theCH3_TX_END_INT interrupt."]
89    #[inline(always)]
90    #[must_use]
91    pub fn ch3_tx_end(&mut self) -> CH3_TX_END_W<INT_CLR_SPEC> {
92        CH3_TX_END_W::new(self, 3)
93    }
94    #[doc = "Bit 4 - Set this bit to clear theCH0_ERR_INT interrupt."]
95    #[inline(always)]
96    #[must_use]
97    pub fn tx_ch0_err(&mut self) -> TX_CH0_ERR_W<INT_CLR_SPEC> {
98        TX_CH0_ERR_W::new(self, 4)
99    }
100    #[doc = "Bit 5 - Set this bit to clear theCH1_ERR_INT interrupt."]
101    #[inline(always)]
102    #[must_use]
103    pub fn tx_ch1_err(&mut self) -> TX_CH1_ERR_W<INT_CLR_SPEC> {
104        TX_CH1_ERR_W::new(self, 5)
105    }
106    #[doc = "Bit 6 - Set this bit to clear theCH2_ERR_INT interrupt."]
107    #[inline(always)]
108    #[must_use]
109    pub fn tx_ch2_err(&mut self) -> TX_CH2_ERR_W<INT_CLR_SPEC> {
110        TX_CH2_ERR_W::new(self, 6)
111    }
112    #[doc = "Bit 7 - Set this bit to clear theCH3_ERR_INT interrupt."]
113    #[inline(always)]
114    #[must_use]
115    pub fn tx_ch3_err(&mut self) -> TX_CH3_ERR_W<INT_CLR_SPEC> {
116        TX_CH3_ERR_W::new(self, 7)
117    }
118    #[doc = "Bit 8 - Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt."]
119    #[inline(always)]
120    #[must_use]
121    pub fn ch0_tx_thr_event(&mut self) -> CH0_TX_THR_EVENT_W<INT_CLR_SPEC> {
122        CH0_TX_THR_EVENT_W::new(self, 8)
123    }
124    #[doc = "Bit 9 - Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt."]
125    #[inline(always)]
126    #[must_use]
127    pub fn ch1_tx_thr_event(&mut self) -> CH1_TX_THR_EVENT_W<INT_CLR_SPEC> {
128        CH1_TX_THR_EVENT_W::new(self, 9)
129    }
130    #[doc = "Bit 10 - Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt."]
131    #[inline(always)]
132    #[must_use]
133    pub fn ch2_tx_thr_event(&mut self) -> CH2_TX_THR_EVENT_W<INT_CLR_SPEC> {
134        CH2_TX_THR_EVENT_W::new(self, 10)
135    }
136    #[doc = "Bit 11 - Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt."]
137    #[inline(always)]
138    #[must_use]
139    pub fn ch3_tx_thr_event(&mut self) -> CH3_TX_THR_EVENT_W<INT_CLR_SPEC> {
140        CH3_TX_THR_EVENT_W::new(self, 11)
141    }
142    #[doc = "Bit 12 - Set this bit to clear theCH0_TX_LOOP_INT interrupt."]
143    #[inline(always)]
144    #[must_use]
145    pub fn ch0_tx_loop(&mut self) -> CH0_TX_LOOP_W<INT_CLR_SPEC> {
146        CH0_TX_LOOP_W::new(self, 12)
147    }
148    #[doc = "Bit 13 - Set this bit to clear theCH1_TX_LOOP_INT interrupt."]
149    #[inline(always)]
150    #[must_use]
151    pub fn ch1_tx_loop(&mut self) -> CH1_TX_LOOP_W<INT_CLR_SPEC> {
152        CH1_TX_LOOP_W::new(self, 13)
153    }
154    #[doc = "Bit 14 - Set this bit to clear theCH2_TX_LOOP_INT interrupt."]
155    #[inline(always)]
156    #[must_use]
157    pub fn ch2_tx_loop(&mut self) -> CH2_TX_LOOP_W<INT_CLR_SPEC> {
158        CH2_TX_LOOP_W::new(self, 14)
159    }
160    #[doc = "Bit 15 - Set this bit to clear theCH3_TX_LOOP_INT interrupt."]
161    #[inline(always)]
162    #[must_use]
163    pub fn ch3_tx_loop(&mut self) -> CH3_TX_LOOP_W<INT_CLR_SPEC> {
164        CH3_TX_LOOP_W::new(self, 15)
165    }
166    #[doc = "Bit 16 - Set this bit to clear theCH4_RX_END_INT interrupt."]
167    #[inline(always)]
168    #[must_use]
169    pub fn ch4_rx_end(&mut self) -> CH4_RX_END_W<INT_CLR_SPEC> {
170        CH4_RX_END_W::new(self, 16)
171    }
172    #[doc = "Bit 17 - Set this bit to clear theCH5_RX_END_INT interrupt."]
173    #[inline(always)]
174    #[must_use]
175    pub fn ch5_rx_end(&mut self) -> CH5_RX_END_W<INT_CLR_SPEC> {
176        CH5_RX_END_W::new(self, 17)
177    }
178    #[doc = "Bit 18 - Set this bit to clear theCH6_RX_END_INT interrupt."]
179    #[inline(always)]
180    #[must_use]
181    pub fn ch6_rx_end(&mut self) -> CH6_RX_END_W<INT_CLR_SPEC> {
182        CH6_RX_END_W::new(self, 18)
183    }
184    #[doc = "Bit 19 - Set this bit to clear theCH7_RX_END_INT interrupt."]
185    #[inline(always)]
186    #[must_use]
187    pub fn ch7_rx_end(&mut self) -> CH7_RX_END_W<INT_CLR_SPEC> {
188        CH7_RX_END_W::new(self, 19)
189    }
190    #[doc = "Bit 20 - Set this bit to clear theCH4_ERR_INT interrupt."]
191    #[inline(always)]
192    #[must_use]
193    pub fn rx_ch4_err(&mut self) -> RX_CH4_ERR_W<INT_CLR_SPEC> {
194        RX_CH4_ERR_W::new(self, 20)
195    }
196    #[doc = "Bit 21 - Set this bit to clear theCH5_ERR_INT interrupt."]
197    #[inline(always)]
198    #[must_use]
199    pub fn rx_ch5_err(&mut self) -> RX_CH5_ERR_W<INT_CLR_SPEC> {
200        RX_CH5_ERR_W::new(self, 21)
201    }
202    #[doc = "Bit 22 - Set this bit to clear theCH6_ERR_INT interrupt."]
203    #[inline(always)]
204    #[must_use]
205    pub fn rx_ch6_err(&mut self) -> RX_CH6_ERR_W<INT_CLR_SPEC> {
206        RX_CH6_ERR_W::new(self, 22)
207    }
208    #[doc = "Bit 23 - Set this bit to clear theCH7_ERR_INT interrupt."]
209    #[inline(always)]
210    #[must_use]
211    pub fn rx_ch7_err(&mut self) -> RX_CH7_ERR_W<INT_CLR_SPEC> {
212        RX_CH7_ERR_W::new(self, 23)
213    }
214    #[doc = "Bit 24 - Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt."]
215    #[inline(always)]
216    #[must_use]
217    pub fn ch4_rx_thr_event(&mut self) -> CH4_RX_THR_EVENT_W<INT_CLR_SPEC> {
218        CH4_RX_THR_EVENT_W::new(self, 24)
219    }
220    #[doc = "Bit 25 - Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt."]
221    #[inline(always)]
222    #[must_use]
223    pub fn ch5_rx_thr_event(&mut self) -> CH5_RX_THR_EVENT_W<INT_CLR_SPEC> {
224        CH5_RX_THR_EVENT_W::new(self, 25)
225    }
226    #[doc = "Bit 26 - Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt."]
227    #[inline(always)]
228    #[must_use]
229    pub fn ch6_rx_thr_event(&mut self) -> CH6_RX_THR_EVENT_W<INT_CLR_SPEC> {
230        CH6_RX_THR_EVENT_W::new(self, 26)
231    }
232    #[doc = "Bit 27 - Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt."]
233    #[inline(always)]
234    #[must_use]
235    pub fn ch7_rx_thr_event(&mut self) -> CH7_RX_THR_EVENT_W<INT_CLR_SPEC> {
236        CH7_RX_THR_EVENT_W::new(self, 27)
237    }
238    #[doc = "Bit 28 - Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt."]
239    #[inline(always)]
240    #[must_use]
241    pub fn tx_ch3_dma_access_fail(&mut self) -> TX_CH3_DMA_ACCESS_FAIL_W<INT_CLR_SPEC> {
242        TX_CH3_DMA_ACCESS_FAIL_W::new(self, 28)
243    }
244    #[doc = "Bit 29 - Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt."]
245    #[inline(always)]
246    #[must_use]
247    pub fn rx_ch7_dma_access_fail(&mut self) -> RX_CH7_DMA_ACCESS_FAIL_W<INT_CLR_SPEC> {
248        RX_CH7_DMA_ACCESS_FAIL_W::new(self, 29)
249    }
250}
251#[doc = "Interrupt clear bits\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`int_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
252pub struct INT_CLR_SPEC;
253impl crate::RegisterSpec for INT_CLR_SPEC {
254    type Ux = u32;
255}
256#[doc = "`write(|w| ..)` method takes [`int_clr::W`](W) writer structure"]
257impl crate::Writable for INT_CLR_SPEC {
258    type Safety = crate::Unsafe;
259    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
260    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x3fff_ffff;
261}
262#[doc = "`reset()` method sets INT_CLR to value 0"]
263impl crate::Resettable for INT_CLR_SPEC {
264    const RESET_VALUE: u32 = 0;
265}
esp32p4/rmt/int_clr.rs

esp32p4/rmt/
int_clr.rs
