esp32p4/lp_uart/
int_st.rs1#[doc = "Register `INT_ST` reader"]
2pub type R = crate::R<INT_ST_SPEC>;
3#[doc = "Field `RXFIFO_FULL_INT_ST` reader - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
4pub type RXFIFO_FULL_INT_ST_R = crate::BitReader;
5#[doc = "Field `TXFIFO_EMPTY_INT_ST` reader - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
6pub type TXFIFO_EMPTY_INT_ST_R = crate::BitReader;
7#[doc = "Field `PARITY_ERR_INT_ST` reader - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
8pub type PARITY_ERR_INT_ST_R = crate::BitReader;
9#[doc = "Field `FRM_ERR_INT_ST` reader - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."]
10pub type FRM_ERR_INT_ST_R = crate::BitReader;
11#[doc = "Field `RXFIFO_OVF_INT_ST` reader - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
12pub type RXFIFO_OVF_INT_ST_R = crate::BitReader;
13#[doc = "Field `DSR_CHG_INT_ST` reader - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
14pub type DSR_CHG_INT_ST_R = crate::BitReader;
15#[doc = "Field `CTS_CHG_INT_ST` reader - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
16pub type CTS_CHG_INT_ST_R = crate::BitReader;
17#[doc = "Field `BRK_DET_INT_ST` reader - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
18pub type BRK_DET_INT_ST_R = crate::BitReader;
19#[doc = "Field `RXFIFO_TOUT_INT_ST` reader - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
20pub type RXFIFO_TOUT_INT_ST_R = crate::BitReader;
21#[doc = "Field `SW_XON_INT_ST` reader - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
22pub type SW_XON_INT_ST_R = crate::BitReader;
23#[doc = "Field `SW_XOFF_INT_ST` reader - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
24pub type SW_XOFF_INT_ST_R = crate::BitReader;
25#[doc = "Field `GLITCH_DET_INT_ST` reader - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
26pub type GLITCH_DET_INT_ST_R = crate::BitReader;
27#[doc = "Field `TX_BRK_DONE_INT_ST` reader - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
28pub type TX_BRK_DONE_INT_ST_R = crate::BitReader;
29#[doc = "Field `TX_BRK_IDLE_DONE_INT_ST` reader - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
30pub type TX_BRK_IDLE_DONE_INT_ST_R = crate::BitReader;
31#[doc = "Field `TX_DONE_INT_ST` reader - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
32pub type TX_DONE_INT_ST_R = crate::BitReader;
33#[doc = "Field `AT_CMD_CHAR_DET_INT_ST` reader - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
34pub type AT_CMD_CHAR_DET_INT_ST_R = crate::BitReader;
35#[doc = "Field `WAKEUP_INT_ST` reader - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."]
36pub type WAKEUP_INT_ST_R = crate::BitReader;
37impl R {
38 #[doc = "Bit 0 - This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1."]
39 #[inline(always)]
40 pub fn rxfifo_full_int_st(&self) -> RXFIFO_FULL_INT_ST_R {
41 RXFIFO_FULL_INT_ST_R::new((self.bits & 1) != 0)
42 }
43 #[doc = "Bit 1 - This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1."]
44 #[inline(always)]
45 pub fn txfifo_empty_int_st(&self) -> TXFIFO_EMPTY_INT_ST_R {
46 TXFIFO_EMPTY_INT_ST_R::new(((self.bits >> 1) & 1) != 0)
47 }
48 #[doc = "Bit 2 - This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1."]
49 #[inline(always)]
50 pub fn parity_err_int_st(&self) -> PARITY_ERR_INT_ST_R {
51 PARITY_ERR_INT_ST_R::new(((self.bits >> 2) & 1) != 0)
52 }
53 #[doc = "Bit 3 - This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1."]
54 #[inline(always)]
55 pub fn frm_err_int_st(&self) -> FRM_ERR_INT_ST_R {
56 FRM_ERR_INT_ST_R::new(((self.bits >> 3) & 1) != 0)
57 }
58 #[doc = "Bit 4 - This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1."]
59 #[inline(always)]
60 pub fn rxfifo_ovf_int_st(&self) -> RXFIFO_OVF_INT_ST_R {
61 RXFIFO_OVF_INT_ST_R::new(((self.bits >> 4) & 1) != 0)
62 }
63 #[doc = "Bit 5 - This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1."]
64 #[inline(always)]
65 pub fn dsr_chg_int_st(&self) -> DSR_CHG_INT_ST_R {
66 DSR_CHG_INT_ST_R::new(((self.bits >> 5) & 1) != 0)
67 }
68 #[doc = "Bit 6 - This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1."]
69 #[inline(always)]
70 pub fn cts_chg_int_st(&self) -> CTS_CHG_INT_ST_R {
71 CTS_CHG_INT_ST_R::new(((self.bits >> 6) & 1) != 0)
72 }
73 #[doc = "Bit 7 - This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1."]
74 #[inline(always)]
75 pub fn brk_det_int_st(&self) -> BRK_DET_INT_ST_R {
76 BRK_DET_INT_ST_R::new(((self.bits >> 7) & 1) != 0)
77 }
78 #[doc = "Bit 8 - This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1."]
79 #[inline(always)]
80 pub fn rxfifo_tout_int_st(&self) -> RXFIFO_TOUT_INT_ST_R {
81 RXFIFO_TOUT_INT_ST_R::new(((self.bits >> 8) & 1) != 0)
82 }
83 #[doc = "Bit 9 - This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1."]
84 #[inline(always)]
85 pub fn sw_xon_int_st(&self) -> SW_XON_INT_ST_R {
86 SW_XON_INT_ST_R::new(((self.bits >> 9) & 1) != 0)
87 }
88 #[doc = "Bit 10 - This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1."]
89 #[inline(always)]
90 pub fn sw_xoff_int_st(&self) -> SW_XOFF_INT_ST_R {
91 SW_XOFF_INT_ST_R::new(((self.bits >> 10) & 1) != 0)
92 }
93 #[doc = "Bit 11 - This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1."]
94 #[inline(always)]
95 pub fn glitch_det_int_st(&self) -> GLITCH_DET_INT_ST_R {
96 GLITCH_DET_INT_ST_R::new(((self.bits >> 11) & 1) != 0)
97 }
98 #[doc = "Bit 12 - This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1."]
99 #[inline(always)]
100 pub fn tx_brk_done_int_st(&self) -> TX_BRK_DONE_INT_ST_R {
101 TX_BRK_DONE_INT_ST_R::new(((self.bits >> 12) & 1) != 0)
102 }
103 #[doc = "Bit 13 - This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1."]
104 #[inline(always)]
105 pub fn tx_brk_idle_done_int_st(&self) -> TX_BRK_IDLE_DONE_INT_ST_R {
106 TX_BRK_IDLE_DONE_INT_ST_R::new(((self.bits >> 13) & 1) != 0)
107 }
108 #[doc = "Bit 14 - This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1."]
109 #[inline(always)]
110 pub fn tx_done_int_st(&self) -> TX_DONE_INT_ST_R {
111 TX_DONE_INT_ST_R::new(((self.bits >> 14) & 1) != 0)
112 }
113 #[doc = "Bit 18 - This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1."]
114 #[inline(always)]
115 pub fn at_cmd_char_det_int_st(&self) -> AT_CMD_CHAR_DET_INT_ST_R {
116 AT_CMD_CHAR_DET_INT_ST_R::new(((self.bits >> 18) & 1) != 0)
117 }
118 #[doc = "Bit 19 - This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1."]
119 #[inline(always)]
120 pub fn wakeup_int_st(&self) -> WAKEUP_INT_ST_R {
121 WAKEUP_INT_ST_R::new(((self.bits >> 19) & 1) != 0)
122 }
123}
124#[cfg(feature = "impl-register-debug")]
125impl core::fmt::Debug for R {
126 fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
127 f.debug_struct("INT_ST")
128 .field(
129 "rxfifo_full_int_st",
130 &format_args!("{}", self.rxfifo_full_int_st().bit()),
131 )
132 .field(
133 "txfifo_empty_int_st",
134 &format_args!("{}", self.txfifo_empty_int_st().bit()),
135 )
136 .field(
137 "parity_err_int_st",
138 &format_args!("{}", self.parity_err_int_st().bit()),
139 )
140 .field(
141 "frm_err_int_st",
142 &format_args!("{}", self.frm_err_int_st().bit()),
143 )
144 .field(
145 "rxfifo_ovf_int_st",
146 &format_args!("{}", self.rxfifo_ovf_int_st().bit()),
147 )
148 .field(
149 "dsr_chg_int_st",
150 &format_args!("{}", self.dsr_chg_int_st().bit()),
151 )
152 .field(
153 "cts_chg_int_st",
154 &format_args!("{}", self.cts_chg_int_st().bit()),
155 )
156 .field(
157 "brk_det_int_st",
158 &format_args!("{}", self.brk_det_int_st().bit()),
159 )
160 .field(
161 "rxfifo_tout_int_st",
162 &format_args!("{}", self.rxfifo_tout_int_st().bit()),
163 )
164 .field(
165 "sw_xon_int_st",
166 &format_args!("{}", self.sw_xon_int_st().bit()),
167 )
168 .field(
169 "sw_xoff_int_st",
170 &format_args!("{}", self.sw_xoff_int_st().bit()),
171 )
172 .field(
173 "glitch_det_int_st",
174 &format_args!("{}", self.glitch_det_int_st().bit()),
175 )
176 .field(
177 "tx_brk_done_int_st",
178 &format_args!("{}", self.tx_brk_done_int_st().bit()),
179 )
180 .field(
181 "tx_brk_idle_done_int_st",
182 &format_args!("{}", self.tx_brk_idle_done_int_st().bit()),
183 )
184 .field(
185 "tx_done_int_st",
186 &format_args!("{}", self.tx_done_int_st().bit()),
187 )
188 .field(
189 "at_cmd_char_det_int_st",
190 &format_args!("{}", self.at_cmd_char_det_int_st().bit()),
191 )
192 .field(
193 "wakeup_int_st",
194 &format_args!("{}", self.wakeup_int_st().bit()),
195 )
196 .finish()
197 }
198}
199#[cfg(feature = "impl-register-debug")]
200impl core::fmt::Debug for crate::generic::Reg<INT_ST_SPEC> {
201 fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
202 core::fmt::Debug::fmt(&self.read(), f)
203 }
204}
205#[doc = "Masked interrupt status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`int_st::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
206pub struct INT_ST_SPEC;
207impl crate::RegisterSpec for INT_ST_SPEC {
208 type Ux = u32;
209}
210#[doc = "`read()` method returns [`int_st::R`](R) reader structure"]
211impl crate::Readable for INT_ST_SPEC {}
212#[doc = "`reset()` method sets INT_ST to value 0"]
213impl crate::Resettable for INT_ST_SPEC {
214 const RESET_VALUE: u32 = 0;
215}