esp32p4/lp_io_mux/
ext_wakeup0_sel.rs

1#[doc = "Register `EXT_WAKEUP0_SEL` reader"]
2pub type R = crate::R<EXT_WAKEUP0_SEL_SPEC>;
3#[doc = "Register `EXT_WAKEUP0_SEL` writer"]
4pub type W = crate::W<EXT_WAKEUP0_SEL_SPEC>;
5#[doc = "Field `REG_XTL_EXT_CTR_SEL` reader - select LP GPIO 0 ~ 15 to control XTAL"]
6pub type REG_XTL_EXT_CTR_SEL_R = crate::FieldReader;
7#[doc = "Field `REG_XTL_EXT_CTR_SEL` writer - select LP GPIO 0 ~ 15 to control XTAL"]
8pub type REG_XTL_EXT_CTR_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
9#[doc = "Field `REG_EXT_WAKEUP0_SEL` reader - Reserved"]
10pub type REG_EXT_WAKEUP0_SEL_R = crate::FieldReader;
11#[doc = "Field `REG_EXT_WAKEUP0_SEL` writer - Reserved"]
12pub type REG_EXT_WAKEUP0_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
13impl R {
14    #[doc = "Bits 0:4 - select LP GPIO 0 ~ 15 to control XTAL"]
15    #[inline(always)]
16    pub fn reg_xtl_ext_ctr_sel(&self) -> REG_XTL_EXT_CTR_SEL_R {
17        REG_XTL_EXT_CTR_SEL_R::new((self.bits & 0x1f) as u8)
18    }
19    #[doc = "Bits 5:9 - Reserved"]
20    #[inline(always)]
21    pub fn reg_ext_wakeup0_sel(&self) -> REG_EXT_WAKEUP0_SEL_R {
22        REG_EXT_WAKEUP0_SEL_R::new(((self.bits >> 5) & 0x1f) as u8)
23    }
24}
25#[cfg(feature = "impl-register-debug")]
26impl core::fmt::Debug for R {
27    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
28        f.debug_struct("EXT_WAKEUP0_SEL")
29            .field(
30                "reg_xtl_ext_ctr_sel",
31                &format_args!("{}", self.reg_xtl_ext_ctr_sel().bits()),
32            )
33            .field(
34                "reg_ext_wakeup0_sel",
35                &format_args!("{}", self.reg_ext_wakeup0_sel().bits()),
36            )
37            .finish()
38    }
39}
40#[cfg(feature = "impl-register-debug")]
41impl core::fmt::Debug for crate::generic::Reg<EXT_WAKEUP0_SEL_SPEC> {
42    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
43        core::fmt::Debug::fmt(&self.read(), f)
44    }
45}
46impl W {
47    #[doc = "Bits 0:4 - select LP GPIO 0 ~ 15 to control XTAL"]
48    #[inline(always)]
49    #[must_use]
50    pub fn reg_xtl_ext_ctr_sel(&mut self) -> REG_XTL_EXT_CTR_SEL_W<EXT_WAKEUP0_SEL_SPEC> {
51        REG_XTL_EXT_CTR_SEL_W::new(self, 0)
52    }
53    #[doc = "Bits 5:9 - Reserved"]
54    #[inline(always)]
55    #[must_use]
56    pub fn reg_ext_wakeup0_sel(&mut self) -> REG_EXT_WAKEUP0_SEL_W<EXT_WAKEUP0_SEL_SPEC> {
57        REG_EXT_WAKEUP0_SEL_W::new(self, 5)
58    }
59}
60#[doc = "Reserved\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ext_wakeup0_sel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ext_wakeup0_sel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
61pub struct EXT_WAKEUP0_SEL_SPEC;
62impl crate::RegisterSpec for EXT_WAKEUP0_SEL_SPEC {
63    type Ux = u32;
64}
65#[doc = "`read()` method returns [`ext_wakeup0_sel::R`](R) reader structure"]
66impl crate::Readable for EXT_WAKEUP0_SEL_SPEC {}
67#[doc = "`write(|w| ..)` method takes [`ext_wakeup0_sel::W`](W) writer structure"]
68impl crate::Writable for EXT_WAKEUP0_SEL_SPEC {
69    type Safety = crate::Unsafe;
70    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
71    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
72}
73#[doc = "`reset()` method sets EXT_WAKEUP0_SEL to value 0"]
74impl crate::Resettable for EXT_WAKEUP0_SEL_SPEC {
75    const RESET_VALUE: u32 = 0;
76}
esp32p4/lp_io_mux/ext_wakeup0_sel.rs

esp32p4/lp_io_mux/
ext_wakeup0_sel.rs
